Abstract: An electronic messaging system and method with reduced traceability. An electronic message is separated into a message content and container (header) information. In one aspect, the message content and header information are displayed separately. In another aspect, an electronic message is permanently automatically deleted from the system at a predetermined time.

Abstract: A system and method for performing high speed memory diagnostics via built-in-self-test (BIST). A test system includes a tester for testing an integrated circuit that includes a BIST circuit and a test control circuit. The BIST circuit further includes a BIST engine and fail logic for testing an imbedded memory array. The test control circuit includes three binary up/down counters, a variable delay, and a comparator circuit. A method includes presetting the counters of the test control circuit, presetting the variable delay to a value that is equal to the latency of the fail logic, setting the BIST cycle counter to decrement mode, presetting the variable delay to zero, re-executing the test algorithm, performing a second test operation of capturing the fail data, and performing a third test operation of transmitting the fail data to the tester.

Abstract: An electrostatic-discharge protection circuit having a low level of current leakage from a first power supply to a second power supply. An example protection circuit includes a timing element that electrically decouples the first and second power supplies. Another example protection circuit includes two transistors connected via a node that is electrically decoupled from the second power supply.

Abstract: A semiconductor wafer is provided with one or more parameter scaling metric (PSM) groupings. Each PSM grouping includes a first device having a known active region geometry and further includes a set of one or more devices having active region geometry dimensions in a known relationship with the active region geometry of the first device. One or more parameter scaling metrics are calculated using measured values of one or more active region parameters of interest. The parameter scaling metric(s) can be used to quantify the stability and uniformity of a fabrication process used to make the semiconductor wafer.

Abstract: A system and method for automatically generating a computation mesh for use with an analytical tool, the computation mesh having a plurality of ?-grid lines and ?-grid lines intersecting at grid points positioned with respect to an inner boundary and an outer boundary. The method includes receiving from a user information corresponding to a shape to be analyzed using the analytical tool and solving one or more mesh equation for a plurality of point locations, the one or more mesh equations depending on a source Jacobian scaling parameter that is not equal to 2.

Abstract: A system and method for automatically generating a computation mesh for use with an analytical tool, the computation mesh having a plurality of ?-grid lines and ?-grid lines intersecting at grid points positioned with respect to an inner boundary and an outer boundary. The method includes receiving from a user information corresponding to a shape to be analyzed using the analytical tool and solving one or more mesh equation for a plurality of point locations, the one or more mesh equations depending on a source decay factor that is inversely proportional to the number of ?-grid lines.

Abstract: An on-chip clock multiplier for outputting a fast clock that is approximately a predetermined multiple n of a slow clock. The multiplier utilizing a high-speed oscillator to generate a high-frequency base signal. A lower frequency signal is generated using the high-frequency base signal as a function of the output of a rollover counter that counts from a seed value to a terminal value. A saturation counter is used to determine whether no more than n pulses of the lower frequency signal occur within a single cycle of the slow clock. If not, the lower frequency signal is iteratively slowed by changing the seed value until no more than n pulses of the lower frequency signal occur within a single cycle of the slow clock. When this iteration is done, the fast clock having a frequency that is approximately n times the frequency of the slow clock is output.

Abstract: An integrated circuit that includes a gate control voltage generator that supplies a current control gate voltage to a plurality of current control devices of a corresponding plurality of dynamic logic circuits each having a keeper circuit. The gate control voltage generator provides, via current control gate voltage, global control of the amount of keeper current flowing through the keeper circuits so as to enhance the performance of the dynamic logic circuits.

Abstract: A design structure for an on-chip real-time moisture detection circuitry for monitoring ingress of moisture into an integrated circuit chip during the operational lifetime of the chip. The moisture detection circuitry includes one or more moisture-sensing units and a common moisture monitor for monitoring the state of each moisture-sensing units. The moisture monitor can be configured to provided a real-time moisture-detected signal for signaling that moisture ingress into the integrated circuit chip has occurred.

Abstract: A method of calculating an electron resonance spectra data value for each of one or more chemical constituents. In one embodiment, one or more potential electron capture orbitals is identified for each of the one or more chemical constituents; an electron orbital wavefunction is determined for each of the one or more potential electron capture Orbitals; and a theoretical electron resonance spectra data value is generated for each of the one or more chemical constituents. In another embodiment, a theoretical electron resonance spectra data value may be used to identify an unknown chemical constituent.

Abstract: A hybrid GENERAL MOTORS 4L80E torque converter and a method of converting a GENERAL MOTORS 4T40E torque converter core into the present hybrid GENERAL MOTORS 4L80E torque converter for high performance applications. The present invention includes GENERAL MOTORS 4L80E compatible parts, which are provided in a race kit format to complete the conversion. The present kit includes a hybrid impeller hub, a hybrid turbine hub, a hybrid one-way roller clutch, a hybrid front cover pilot, an adapter ring, a thrust washer, and a set of machine screws. In a method of the present invention the GENERAL MOTORS 4T40E torque converter core undergoes multiple machining operations to remove the original equipment impeller hub, turbine hub, and front cover pilot from the GENERAL MOTORS 4T40E torque converter core, which are each replaced by their counterparts in the present race kit to complete the conversion to the hybrid GENERAL MOTORS 4L80E torque converter.

Abstract: An integrated redundancy architecture for an embedded memory system whereby a third memory element is added to the redundancy architecture such that all row and column fails may be stored in real-time. Architecture (20) includes a first memory element (22) (FME 22) having a register (24), a second memory element (26) (SME 26) having a register (28), a third memory element (30) (TME 30) having a register (32), and a finite state machine (34) (FSM 34) having a decision algorithm (36). FME (22), SME (26), TME (30), and FSM (34) are electrically connected to a built-in self-test (BIST) module (38). BIST module (38) outputs failed row and column addresses (40), also referred to as “fails,” for rows and columns that are identified as defective during the BIST to the memory elements and FSM (34). FSM (34) allocates redundancy resources of the memory system according to decision algorithm (36).

Abstract: An apparatus for locating a magnet and/or determining the orientation of the apparatus relative to the magnet. In one embodiment, the apparatus includes a multi-axis magnetic field sensor movable in a reciprocating manner so as to permit sensor readings at multiple spaced locations. In another embodiment, the apparatus includes a plurality of multi-axis magnetic field sensors arrayed along a straight line. The apparatus may be used in a number of medical and other applications, including tissue resection, tracking movement of a medical device in a body cavity and tracking movement of an internal organ.

Abstract: A snow sled comprising a seating portion that includes a lightweight space frame having a suspension-type seat stretched among the space frame. The sled further includes a steering portion and articulated steering mechanism that links the steering portion to the seating portion. The articulated steering mechanism allows the steering portion to be pivoted laterally relative to the seating portion so as to make the sled readily steerable. A pair of rear skis are removably attachable to the seating portion. The steering portion includes a ski support and a pair of front skis pivotably attached to the ski support. Chatter and movement of the front skis are dampened by a pair of boots that engage the ski support and the respective front skis.

Abstract: An electronic weighing scale that includes an inner housing and an outer housing surrounding the inner housing. In one embodiment, the inner and outer housings are not secured to one another and are spaced apart by shock-absorbing spacers designed to absorb shock of impact loads such as may be caused by the scale being dropped. The inner housing includes a chassis defining a load cell cavity that contains a load cell. The inner housing also includes an electronics compartment closure that together with the chassis define an electronics compartment that contains electronics of the scale, including display electronics and user-controls electronics. In one embodiment, the electronics compartment is hermetically sealed to protect the electronics from moisture.

Abstract: A time-phased forecasting and replenishment system (20) for a retail supply chain for inventory management, financial management, capacity planning and transportation planning. A computer(s) (28) create time-phased plans for one or more retail facilities, such as various types of retail stores (23) and/or various types of suppliers (24). The system calculates projected sales for each product at each facility and calculates projected replenishment shipments between facilities and suppliers a specified number of weeks into the future. The calculated forecasts and replenishments are done in ways that account for the unique needs of retail organizations, and allow efficient processing and storage of the large data volumes typical in many retail organizations. In particular the system has specified logic for handling low-volume products, and has a transportation and capacity planning component that benefits retail stores. Also, the system is designed to operate on a continuous basis if desired.

Abstract: A garment (1) for providing compressive forces to a torso to help eliminate or reduce swelling caused by an accumulation of lymph fluid in the torso region. An embodiment of the present invention includes an outer covering (10) of compression fabric, wide shoulder straps (22, 24), front and back panels of compression fabric (12, 14, 16, 18), a non-rolling rib band (72), axilla gussets (82, 84), and both front closure (40) and back closure (50). The garment may also include one or more princess seams (102, 104, 102?, 104?) so as to enable the front panel(s) to encapsulate and hold the user's breasts in place at the same time that compressive forces are applied, as well as one or more front shelves (132, 134) in the front panel(s) for providing upward compressive support to the breast tissue, thereby holding the tissue in a proper neutral position so that inward compressive forces acting on the tissue provide maximum effect.

Abstract: Integrated circuit (IC) system architectures that allow for the reduction of on-chip or across-chip transient noise budgets by providing a means to avoid simultaneous high current demand events from at least two functional logic blocks, i.e., noise contributors, are disclosed. Embodiments of the IC systems architectures include at least one noise event arbiter and at least two noise contributor blocks. A method of scheduling on-clip noise events to avoid simultaneous active transient noise events may include, but is not limited to: the noise event arbiter receiving simultaneously multiple requests-to-operate from multiple noise contributers; the noise event arbiter determining when each noise contributer may execute operations based on a pre-established dI/dt budget; and the noise event arbiter notifying each noise contributer as to when permission is granted to execute its operations.

Abstract: A shift register latch (SRL) (300, 304, 400) compatible with performing level sensitive scan design (LSSD) testing with a single scan clock (SCAN CLK) and single scan clock tree (64). The SRL includes a master latch (308, 308?, 404), a slave latch (312, 312?, 408) and a circuit element (328, 328?, 416) connected between the scan clock tree and the master latch. The scan clock generates a clock signal (350, 440) having regularly spaced pulses during the scan phase of the LSSD testing. The circuit element generates a short-pulsed signal (354, 354?) based on the scan clock signal for triggering the master latch.

Abstract: A frequency coincidence detection circuit for detecting frequency edges for each of a plurality of periodic digital signals. The circuit generates count indicators for each of the periodic digital signals and compares each of the count indicators to a programmable sensitivity input to determine a coincidence window for the corresponding one of each of the periodic digital signals. The circuit determines a signal coincidence of the coincidence windows. In another embodiment, a frequency coincidence detection method is provided. The method detects frequency edges for each of a plurality of periodic digital signals, generates count indicators for each of the periodic digital signals and compares each of the count indicators to a programmable sensitivity input to determine a coincidence window for the corresponding one of each of the periodic digital signals. The method determines a signal coincidence of the coincidence windows.