Abstract: A compound gear system and method comprising a flexible gear defining an array of gear elements in an articulating relationship, a rigid structure defining first and second spaced parallel pluralities of articulating gear support structures arrayed in a ring, the articulating gear reeved tightly about and engaging the support structures, thereby restraining the flexible articulating gear from moving inwardly or rotationally relative to the rigid structure while enabling the flexible gear to expand outward, and at least one sprocket gear having a plurality of sprocket teeth aligned to engage flexible gear element middle areas. The support structures transmit torque between the flexible gear elements and the rigid structure responsive to interaction of the flexible gear element middle areas with the sprocket gear teeth.

Abstract: Systems, methods and program codes are provided for testing multi-core processor chip structures. Individual processor core power supply voltages are provided through controlling individual power supplies for each core, in one aspect to ensure that one or more cores operate at clock rates in compliance with one or more performance specifications. In one example, a first power supply voltage supplied to a first processing core differs from a second core power supply voltage supplied to a second processing core, both cores operating in compliance with a reference clock rate specification. Core power supply voltages may be selected from ordered discrete supply voltages derived by progressively raising or lowering a first supply voltage, optionally wherein the selected supply voltage also enables the core to operate within another performance specification.

Abstract: This invention is useful in a networked system with densely packaged servers or server blades. The servers are connected to a system management network, a communication network and an image server. A management module attached to the system management network and a network switch monitors and controls network booting from an image server on the communication network to prevent over commitment of network and image server resources in order to avoid a boot storm. The management module collects system information and calculates the number of servers or clients the networked system can boot at any one instant of time without burdening the system. The management module logic controls booting via the system management network and service processor elements, which can block server booting and release servers to boot when other servers have completed their boot process.

Abstract: A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes several control blocks, one for each data buffer, each containing control information linking one buffer to another. Each control block has a last bit feature which is a single bit settable to “one or “zero” and indicates the transmission of when the data buffer having the last bit. The last bit is in a first position when an additional data buffer is to be chained to a previous data buffer indicating an additional data buffer is to be transmitted and a second position when no additional data buffer is to be chained to a previous data buffer. The position of the last bit is communicated to the network processor indicating the ending of a particular frame.

Abstract: A method for inter partition communication within a logical partitioned data processing system where each partition is configured for an inter partition communication area (IPCA) allocated from partition's own system memory. Each partition's IPCA combined together forms a non-contiguous block of memory which is treated as a virtual shared resource (VSR). Access to VSR is controlled by hypervisor to maintain data security and coherency of the non-shared resources of a partition. Messages are written to and read from VSR under a specific partition's IPCA for inter partition communication. No physical shared or non-shared resources are involved during inter partition communication, hence no extra overhead on those resources, thus achieving optimized performance during inter partition communication.

Abstract: A high speed serial data communication system includes provisions for the correction of equalization errors, particularly those errors introduced by equalizer non-idealities. The equalization is achieved at the data transmitter, and is based on dynamic current subtraction at the output of a differential pair. When bit time>0, the error current is removed or subtracted from the total driver current, thereby maintaining a constant total current from bit time 0 to bit time>0. The same result can also be achieved by subtracting current when bit time>0 using field effect transistors of the opposite gender. The error current can be determined empirically from simulation or through feedback using a replica of the driver. The circuits for achieving equalization error correction and the resulting electrical network analysis are shown and described.

Abstract: A method and structure is disclosed for dispatching appropriate data to a network processing system comprising an improved technique for extracting protocol header fields for use by the network processor. This technique includes basic classification of a packet according to the types of protocol headers present in the packet. Based on the results of the classification, specific parameter fields are extracted from corresponding headers. All such parameter fields from one or more protocol headers in the packet are concatenated into a compressed dispatch message. Multiple of such dispatch messages are bundled into a single composite dispatch message. Thus selected header fields from N packets are passed to the network processor in a single composite dispatch message, increasing the network processor's packet forwarding capacity by a factor of N. Likewise, multiple enqueue messages are bundled into a single composite enqueue message to direct enqueue and frame alterations to be taken on the bundle of N packets.

Abstract: The present invention allows the contents of network-wide broadcast in a first subnetwork to be passed to a second subnetwork even if a router is set to prevent the network-wide broadcast in the first subnetwork from going out of the first subnetwork. In response to the network-wide broadcast in the first subnetwork, a first broadcast relay generates a packet in which a destination address of the network-wide broadcast packet is changed to an address of a second broadcast relay belonging to a second subnetwork, and outputs the address changed packet to the first subnetwork. The second broadcast relay generates, in response to the packet addressed thereto, a second subnetwork-only broadcast as a local broadcast, and outputs it to the second subnetwork. A server of the second subnetwork performs a predetermined process on the broadcast outputted by the second broadcast relay.

Abstract: A method and system comprising a diagnostic symptom tree system for diagnosing a failing system element causing a symptom in a system-under-test. A diagnostic symptom tree comprises symptom roots and dependent lower function nodes and sub-function nodes. Element nodes depend from the function or sub-function nodes, and a plurality of penultimate failure mode leaves depend from the element nodes. The function and sub-function nodes and the failure mode leaves comprise test information. Responsive to positive test results, the diagnostic symptom tree is configured to identify a function or sub-function or element node associated to a lowest symptom tree node or failure mode leaf for which a test is positive, or advise that no failing function or sub-function or element is found. In one aspect of the invention, nodes may include parameter values allowing successive selections of the nodes of the symptom tree for test iterations according to the parameter values.

Abstract: A method and structure is provided for buffering data packets having a header and a remainder in a network processor system. The network processor system has a processor on a chip and at least one buffer on the chip. Each buffer on the chip is configured to buffer the header of the packets in a preselected order before execution in the processor, and the remainder of the packet is stored in an external buffer apart from the chip. The method comprises utilizing the header information to identify the location and extent of the remainder of the packet. The entire selected packet is stored in the external buffer when the buffer of the stored header of the given packet is full, and moving only the header of a selected packet stored in the external buffer to the buffer on the chip when the buffer on the chip has space therefor.

Abstract: A structure and technique for preventing collisions using a hash table in conjunction with a CAM to identify and prevent collision of binary keys. A portion of the hash value of a binary key, which does not collide with a portion of the hash value of any other reference binary key, is used as an entry in the hash table. If two or more binary keys have identical values of the portions of the hash values, each of these binary keys are stored in their entirety, in the CAM. The key in the CAM provides a pointer to a data structure where the action associated with that binary key is stored. If the binary key is not found in the CAM, the binary key is hashed, and a specific entry in the hash table is selected using a portion of this hash value.

Abstract: A method of forming a core for and forming a composite wiring board. The core has an electrically conductive coating on at least one face of a dielectric substrate. At least one opening is formed through the substrate extending from one face to the other and through each conductive coating. An electrically conductive material is dispensed in each of the openings extending through the conducting coating. At least a portion of the surface of the conductive coating on one face is removed to allow a nub of the conductive material to extend above the substrate face and any remaining conductive material to thereby form a core that can be electrically joined face-to-face with a second core member or other circuitized structure.

Abstract: The present invention provides a method and system of accessing at least one target file in a computer system with an operating system with file locking implemented with byte-range locking. In an exemplary embodiment, the method and system include obtaining a set of handles that corresponds to a set of all files that are open in the computer system, determining within the kernel of the operating system a set of file identifiers that corresponds to the set of handles, identifying from the set of file identifiers a file identifier that corresponds to the target file, sending the identified file identifier to the kernel, initializing within the kernel file caching for the identified file identifier, and requesting within the kernel the cache manager of the operating system to obtain by using the identified file identifier a region of the target file from the file system driver of the operating system.

Abstract: A stump grinding apparatus having a split cutting wheel includes several replaceable cutter blocks secured to the periphery of the wheel. One or more replacement teeth are removably anchored in holes in each block and may also be mounted on holes in the side of the split wheel as well. The teeth are typically provided with a hardened cutting face, and are reinforced with an extension projecting back from the face. Each tooth includes a shank which fits into one of the holes. The shank contains a groove which receives a spring clip or a spring pin for securing the tooth in the hole. The wheel periphery contains individual recesses that are shaped to receive the cutter blocks. Each block includes means for insuring alignment of the block in the corresponding recess. The block is wedged tightly into its recess to reduce the likelihood of accidental removal.

Abstract: A Local Dynamic Power Controller (LDPC) generates and deliver to a load a full swing voltage supply signal and a reduced swing voltage supply signal. Both the full and reduce voltage supply signals are generated from a single power supply. The full swing voltage supply signal is supplied when the load is in full operational mode whereas the reduce voltage supply signal is provided when the load is in a sleep mode. As a consequence, power dissipated in the load is reduced.

Abstract: A method of forming a printed circuit card with a metal power plane layer between two photoimageable dielectric layers is provided. Photoformed metal filled vias and plated through holes are in the photopatternable material, and signal circuitry is on the surfaces of each of the dielectric materials connected to the vias and plated through holes. A border may be around the card including a metal layer terminating in from the edge of one of the dielectric layers. Copper foil with clearance holes is provided. First and second layers of photoimageable curable dielectric material are on opposite sides of the copper. Patterns are developed on the first and second layers of the photoimageable material to reveal the metal layer through vias. Through holes are developed where holes were patterned in both dielectric layers. The surfaces of the photoimageable material, vias and through holes are metallized by copper plating, preferably using photoresist.

Abstract: A detection and response system that generates an Alert if unauthorized scanning is detected on a computer network that includes a look-up table to record state value corresponding to the sequence in which SYN, SYN/ACK and RST packets are observed. A set of algorithms executed on a processing engine adjusts the state value in response to observing the packets. When the state value reaches a predetermined value indicating that all three packets have been seen, the algorithm generates an Alert.