Abstract: Capacitance circuits are provided disposing a lower vertical-native capacitor metal layer above a planar front-end-of-line semiconductor base substrate, planar metal bottom plates spaced a bottom plate distance from the base and top plates above the bottom plates spaced a top plate distance from the base defining metal-insulator-metal capacitors, top plate footprints disposed above the base substrate smaller than bottom plate footprints and exposing bottom plate remainder upper lateral connector surfaces; disposing parallel positive port and negative port upper vertical-native capacitor metal layers over and each connected to top plate and bottom plate upper remainder lateral connector surface. Moreover, electrical connecting of the first top plate and the second bottom plate to the positive port metal layer and of the second top plate and the first bottom to the negative port metal layer impart equal total negative port and positive port metal-insulator-metal capacitor extrinsic capacitance.

Abstract: The present invention relates to a method and computer system device for applying a plurality of rules to data packets within a network computer system. A filter rule decision tree is updated by adding or deleting a rule. If deleting a filter rule then the decision tree is provided to a network data plane processor with an incremental delete of the filter rule. If adding a filter rule then either providing an incremental insertion of the filter rule to the decision tree or rebuilding the first decision tree into a second decision tree responsive to comparing a parameter to a threshold. In one embodiment the parameter and thresholds relate to depth values of the tree filter rule chained branches. In another the parameter and thresholds relate to a total count of rule additions since a building of the relevant tree.

Abstract: A wireless network access point is described which provides the resources of a backbone network to wireless clients. The access point is able to balance loads by deferring association of new clients and thereby directing clients to associate with alternative access points having improved backbone connectivity. Where the client is unable to find an alternative access point, the client will eventually make a second association request to the access point. The access point, in identifying the second association request of the client, proceeds to associate the client in response to the second association request. Specific time limits can be imposed relative to the second association request.

Abstract: A pipeline configuration is described for use in network traffic management for the hardware scheduling of events arranged in a hierarchical linkage. The configuration reduces costs by minimizing the use of external SRAM memory devices. This results in some external memory devices being shared by different types of control blocks, such as flow queue control blocks, frame control blocks and hierarchy control blocks. Both SRAM and DRAM memory devices are used, depending on the content of the control block (Read-Modify-Write or ‘read’ only) at enqueue and dequeue, or Read-Modify-Write solely at dequeue. The scheduler utilizes time-based calendars and weighted fair queueing calendars in the egress calendar design. Control blocks that are accessed infrequently are stored in DRAM memory while those accessed frequently are stored in SRAM.

Abstract: Each of a plurality of partitions within a logical partitioned data processing system is configured for an inter partition communication area (IPCA) allocated from partition's own system memory. Each partition's IPCA combined together forms a non-contiguous block of memory which is treated as a virtual shared resource (VSR). Access to VSR is controlled by hypervisor to maintain data security and coherency of the non-shared resources of a partition. Messages are written to and read from VSR under a specific partition's IPCA for inter partition communication. No physical shared or non-shared resources are involved during inter partition communication, hence no extra overhead on those resources, thus achieving optimized performance during inter partition communication.

Abstract: Access arbiters are used to prioritize read and write access requests to individual memory banks in DRAM memory devices, particularly fast cycle DRAMs. This serves to optimize the memory bandwidth available for the read and the write operations by avoiding consecutive accesses to the same memory bank and by minimizing dead cycles. The arbiter first divides DRAM accesses into write accesses and read accesses. The access requests are divided into accesses per memory bank with a threshold limit imposed on the number of accesses to each memory bank. The write receive packets are rotated among the banks based on the write queue status. The status of the write queue for each memory bank may also be used for system flow control. The arbiter also typically includes the ability to determine access windows based on the status of the command queues, and to perform arbitration on each access window.

Abstract: Systems, methods and program codes are provided for testing multi-core processor chip structures. Individual processor core power supply voltages are provided through controlling individual power supplies for each core, in one aspect to ensure that one or more cores operate at clock rates in compliance with one or more performance specifications. In one example, a first power supply voltage supplied to a first processing core differs from a second core power supply voltage supplied to a second processing core, both cores operating in compliance with a reference clock rate specification. Core power supply voltages may be selected from ordered discrete supply voltages derived by progressively raising or lowering a first supply voltage, optionally wherein the selected supply voltage also enables the core to operate within another performance specification.

Abstract: A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes several control blocks, one for each data buffer, each containing control information linking one buffer to another. Each control block has a last bit feature which is a single bit settable to “one” or “zero” and indicates when the data buffer having the last bit is transmitted. The last bit is in a first position when an additional data buffer is to be chained to a previous data buffer indicating an additional data buffer is to be transmitted and a second position when no additional data buffer is to be chained to a previous data buffer. The position of the last bit is communicated to the network processor indicating the ending of a particular frame.

Abstract: In a random number generator, a first converter converts a first analog noise signal into a random digital clock signal and a second converter samples a second analog noise signal asynchronous to the first analog noise signal in response to the random digital clock signal and generates a random digital number stream. In one aspect, a random number generator output block samples the second converter random digital number stream in response to the random digital clock signal and generates a random number generator block output. In another aspect a pseudo noise source state machine generates the random digital clock signal in response to a first seed generated from the first analog noise signal, a second seed from process variation digital amplifier, and a past machine state.

Abstract: A fluid detection system comprises a liquid sensor, an air pump and an atmospheric pressure sensor encased within an air and water permeable casing defining an enclosed air space. The pressure sensor acquires pressure samples within the casing, the air pump expelling additional gas into the casing. In response to determining a flood-status or a non-flood-status state of the fluid detection system and comparing the samples, a failure of the fluid detection system or an immersion of the fluid detection system in fluid is determined. In some embodiments, failure is determined if a second sample is greater than a first sample in a non-flooded state, and in others immersion is determined if a second sample is greater than a first sample value and the determined state is flooded. In some examples, gas is expelled across a liquid detection surface and a third sample value is acquired.

Abstract: The present invention allows the contents of network-wide broadcast in a first subnetwork to be passed to a second subnetwork even if a router is set to prevent the network-wide broadcast in the first subnetwork from going out of the first subnetwork. In response to the network-wide broadcast in the first subnetwork, a first broadcast relay generates a packet in which a destination address of the network-wide broadcast packet is changed to an address of a second broadcast relay belonging to a second subnetwork, and outputs the address changed packet to the first subnetwork. The second broadcast relay generates, in response to the packet addressed thereto, a second subnetwork-only broadcast as a local broadcast, and outputs it to the second subnetwork. A server of the second subnetwork performs a predetermined process on the broadcast outputted by the second broadcast relay.

Abstract: A removable digital data storage device has a programmable memory controller, a data storage medium and a data destruction means. The memory controller is encoded with a firmware program to provide a computer device driver interface, wherein the firmware program further configures the memory controller to secure data on the medium by querying for a hardware code in response to a data operation request by a computer through the interface and either granting access in response to a hardware code input or, independent of an operational status of the requesting computer, directly instructing the data destruction means to render data residing on the data storage medium unreadable in response to a failure to receive the first hardware code input through the interface.

Abstract: A capacitance circuit assembly mounted on a semiconductor chip, and methods for forming the same, are provided. A plurality of divergent capacitors is provided in a parallel circuit connection between first and second ports, the plurality providing at least one Metal Oxide Silicon Capacitor and at least one Vertical Native Capacitor or Metal-Insulator-Metal Capacitor. An assembly has a vertical orientation, a Metal Oxide Silicon capacitor located at the bottom and defining a footprint, with a middle Vertical Native Capacitor having a plurality of horizontal metal layers, including a plurality of parallel positive plates alternating with a plurality of parallel negative plates. In another aspect, vertically asymmetric orientations provide a reduced total parasitic capacitance.

Abstract: A system and method are used for updating software to include new versions of the software without losing the ability to return to the prior software in the event of flaws or deficiencies in the new version. A framework organizes conversion and reversion codes into major components responsible for conversion of the data entities. The components are ordered based on their dependence on other components first completing their conversions. Each component implements an interface allowing a framework to process sequentially through all components and sequentially retrieve handles for their respective entities, and accessing the version of the entity. The framework processes an ordered set of interfaces representing the conversion/reversion, checks for progressively newer versions. As data structures are changed for a single component, a new version is appended to that component's ordered set of version interfaces. Restart of a conversion or reversion following an interrupt is also provided.

Abstract: Sensors are located on first and second regions of a heat sink, with a portion of the heat sink interposed between the first and second region sensors. The heat sink is connected to a component by an attachment that conducts heat from the component to the heat sink, and a third sensor is located on the component or the attachment with a portion of the attachment disposed between the third sensor and the first and second heat sink region sensors. Temperature readings from the sensors are compared to identify a failing one of the heat sink, the attachment portion, and the component with respect to heat conduction, which includes identifying the interposed heat sink portion as failing in response to a divergence between temperature inputs from the first and second heat sink region sensors. Rate-of-rise temperature readings may also be observed and compared, including to historical values.

Abstract: Systems, methods and program codes are provided for selectively adjusting multi-core processor chip structure individual processor core power supply voltages through controlling individual power supplies for each core, in one aspect to ensure that one or more cores operate at clock rates in compliance with one or more performance specifications. Nominal power supply voltage is supplied to a first processing core, and a second core power supply voltage greater or lower than the nominal power supply voltage is supplied to a second processing core, both cores operating in compliance with a reference clock rate specification. The second power supply voltage may be selected from ordered discrete supply voltages derived by progressively lowering the nominal supply voltage, optionally wherein the selected supply voltage also enables the second core to operate within another performance specification.

Abstract: A computer system which includes a CPU for performing various processes by program control and storage elements which store at least one operating system and a BIOS, wherein upon starting a system, the CPU recognizes the system's own hardware configuration, and starts a selected one operating system stored in the storage elements in accordance with the recognized hardware configuration under the control of the BIOS.

Abstract: Methods, articles and design structures for capacitance circuits are provided disposing a lower vertical-native capacitor metal layer above a planar front-end-of-line semiconductor base substrate, planar metal bottom plates spaced a bottom plate distance from the base and top plates above the bottom plates spaced a top plate distance from the base defining metal-insulator-metal capacitors, top plate footprints disposed above the base substrate smaller than bottom plate footprints and exposing bottom plate remainder upper lateral connector surfaces; disposing parallel positive port and negative port upper vertical-native capacitor metal layers over and each connected to top plate and bottom plate upper remainder lateral connector surface.

Abstract: Data communication in network traffic is modeled in real time and is analyzed using a 2-state Markov modified Poissen process (MMPP). The traffic inter-arrival times for bursty and idle states define a transition window [?1max, ?2min] represented by the boundary values ?1max for the inter-arrival time for bursty traffic, and ?2min for the inter-arrival time for idle traffic. Changes in the values of ?1max and ?2min are tracked over time, and the size of the transition window is enlarged or decreased based upon relative changes in these values. If the inter-rival times for the bursty state and the idle state become approximately equal, the model defaults to a single state model. The modeling is applicable to the synchronization of polling and blocking in a low-latency network system. This permits the adoptive selection of poll or block to maximize CPU utilization and interrupt latency.