Abstract: Techniques a race logic analysis on an integrated circuit (IC) design are described herein. In one embodiment, all hardware description language (HDL) defined system functions and/or tasks that have one or more side-effects when invoked in a first HDL language, but not when the same HDL-defined system functions/tasks are invoked in a second HDL language are identified. For all processing blocks that invoke the HDL-defined system functions/tasks that have side-effects, one or more triggering conditions of the processing blocks and HDL languages in which the processing blocks are coded are collected. When detecting a concurrent invocation race of the HDL-defined system functions/tasks statically or dynamically, checking is performed only the processing blocks that are coded in one or more HDL languages which render the HDL-defined system functions/tasks to manifest the one or more side-effects. Other methods and apparatuses are also described.