Abstract: A controller shareable by a plurality of operating system domains (OSDs) for communication on a network is disclosed. The controller includes a port for coupling to the network. The port transceives packets with the network for each of the plurality of OSDs. The controller also includes a plurality of replicated programming interfaces that each receive from a respective one of the plurality of OSDs a request to obtain a port ID for the port from the network. The controller obtains from the network a distinct port ID for each of the plurality of OSDs in response to the respective request. The request comprises one or more load-store transactions. In one embodiment, the controller is a shared Fiber Channel controller.

Abstract: A Fibre Channel controller shareable by a plurality of operating system domains (OSDs) is disclosed. The controller includes a programming interface, located within a system load-store memory map of each OSD by which the OSDs request the controller to perform I/O operations with remote FC devices. The programming interface includes a distinct control/status register (CSR) bank for each of OSD. The OSDs execute load-store instructions addressed to the programming interface to request the I/O operations. Selection logic selects as a target of each of the load-store transactions the distinct CSR bank for the OSD that executed the corresponding load-store instruction. An FC port obtains a distinct FC port identifier for each OSD and transceives FC frames with the remote FC devices using the distinct FC port identifier for each OSD in response to the I/O operation requests. In one embodiment, multiple blade servers share the controller via a shared I/O switch.

Abstract: A battery-backed write-caching mass storage controller is disclosed. The controller includes a plurality of volatile memory banks for caching write data prior to being written to disk drives. Critical data is stored into a first subset of the memory banks, leaving a second subset of memory banks storing only non-critical data. Critical data is data that must be retained during a main power loss to avoid loss of write-cached user data. Critical data includes the write-cached user data itself, as well as metadata describing the write-cached user data. When the controller detects a loss of main power, the controller causes the critical memory banks to receive battery power, but disables battery power to the non-critical memory banks in order to extend the length of time the critical memory banks can continue to receive battery power to reduce the likelihood of user data loss.

Abstract: A storage controller has a capacitor pack for storing energy to supply during a main power loss, a temperature sensor that senses the capacitor pack temperature, and a CPU, which repeatedly: receives the temperature during an interval over which the capacitor pack is operated, determines a lifetime over which the capacitor pack would have a capacity to store at least a predetermined amount of energy if operated at the temperature during the lifetime, normalizes the interval by a ratio of a warranted lifetime of the capacitor pack relative to the determined lifetime, and adds the normalized interval to an accumulated normalized running time. The operating voltage of the capacitor pack may also sampled and used to determine the lifetime. The predetermined amount of energy may be for backing up a volatile write cache to a non-volatile memory in response to the loss of main power.

Abstract: A microprocessor for generating a packed sum of absolute differences is disclosed. The microprocessor includes an instruction translator, for translating a Multimedia Extensions (MMX) Packed Sum of Absolute Differences Byte to Word (PSADBW) macroinstruction into at least first and second microinstructions. The microprocessor includes an MMX unit, coupled to the instruction translator, for generating a result of the PSADBW macroinstruction in response to the at least first and second microinstructions.

Abstract: A method for transferring data within a network storage appliance is disclosed. The method includes transmitting a packet on an I/O link from a server to a first portion of a storage controller. Transmitting the packet on the I/O link is performed within a single blade module in a chassis enclosing the storage appliance. The method also includes forwarding a data transfer command within the packet from the first portion of the storage controller to a second portion of the storage controller. Forwarding the data transfer command is performed via a local bus on a backplane of the chassis through a connector of the blade connecting the blade to the backplane.

Abstract: A server blade includes a printed circuit board (PCB), including a connector for connecting the blade to a backplane comprising a local bus, and a removal mechanism for use by a person to disconnect the connector from the backplane for removal of the blade from a chassis while the chassis is powered up. The server blade also includes an I/O link and a server, each affixed on the PCB. The server transmits packets on the I/O link to a storage controller enclosed in the chassis. The packets include commands to transfer data to at least one storage device controlled by the storage controller. A portion of the storage controller, affixed on the PCB, receives the packets from the server on the I/O link, and forwards the commands on the backplane local bus to another portion of the storage controller affixed on a separate PCB enclosed in the chassis.

Abstract: A high data availability write-caching storage controller has a volatile memory with a write cache for caching write cache data, a non-volatile memory, a capacitor pack for supplying power for backing up the write cache to the non-volatile memory in response to a loss of main power, and a CPU that determines whether reducing an operating voltage of the capacitor pack to a new value would cause the capacitor pack to be storing less energy than required for backing up the current size write cache to the non-volatile memory. If so, the CPU reduces the size of the write cache prior to reducing the operating voltage. The CPU estimates the capacity of the capacitor pack to store the required energy based on a history of operational temperature and voltage readings of the capacitor pack, such as on an accumulated normalized running time and warranted lifetime of the capacitor pack.

Abstract: A network storage appliance includes a chassis, enclosing a storage controller and first and second servers. The storage controller has first and second I/O ports for coupling to first and second I/O links. The storage controller controls a plurality of physical disk drives and presents the plurality of physical disk drives as one or more logical disk drives on the first and second I/O links. The servers each have an I/O port for coupling to a respective one of the first and second I/O links. Each of the servers transmits packets to the storage controller over the respective I/O link. The packets include block-level protocol disk commands each identifying one of the logical disk drives, such as SCSI block level protocol commands each identifying one of said logical disk drives as a SCSI logical unit. The I/O links may be FibreChannel, Ethernet, or Infiniband links, for example.

Abstract: A transaction switch and integrated circuit incorporating said for switching data through a shared memory between a plurality of data interfaces that support different data protocols, namely packetized interfaces like InfiniBand and addressed data interfaces like PCI. The transaction switch also switches transactions commanding data transfers between the disparate protocol data interfaces and between those of the data interfaces having like protocols. For example, the transaction switch enables a hybrid InfiniBand channel adapter/switch to perform both InfiniBand packet to local bus protocol data transfers through the shared memory as well as InfiniBand packet switching between the multiple InfiniBand interfaces. The transactions are tailored for each interface type to include information needed by the particular interface type to perform a data transfer.

Abstract: An apparatus for deterministically killing one of redundant servers integrated into a network storage appliance chassis along with at least one storage controller is disclosed. Each server can generate a kill signal on a backplane of the chassis to the other server in response to a stopped heartbeat of the other server in order to disable the I/O ports of the other server on a network so the live server can reliably take over the identity of the other server on the network. Unlike conventional kill paths, such as an Ethernet cable connecting the two servers in separate chassis, the present invention does not require the failed server to be operational since the kill path is substantially a direct reset to the I/O ports of the failed server. One server raises a shield before killing the other server to avoid both servers killing each other simultaneously.

Abstract: An apparatus and method in a pipelined microprocessor for replacing one of two target addresses in a branch target address cache (BTAC) line. If only one of the two entries is invalid, the invalid entry is replaced. If both entries are valid, the least recently used entry is replaced. If both entries are invalid, the entry is replaced corresponding to the side of the BTAC, indicated by a global status register, not last written to with an invalid entry. In one embodiment, the global status is updated only if a side is written when both entries are invalid. In another embodiment, the BTAC stores N entries per line, where N is greater than 1. The status register maintains information for determining which of the N sides is least recently written. The least recently written side is chosen for replacement.

Abstract: An apparatus in a microprocessor for selectively retiring a prefetched cache line is disclosed. The microprocessor includes a prefetch buffer that stores a cache line prefetched from a system memory coupled to the microprocessor. The microprocessor includes a cache memory, comprising an array of storage elements for storing cache lines. The array is indexed by an index input. The microprocessor includes a counter that counts a number of accesses to a replacement candidate line in the cache. The replacement candidate line is stored in a storage element of the array indexed by an index portion of an address of the prefetched cache line stored in the prefetch buffer. The microprocessor also includes control logic that selectively replaces the replacement candidate cache line in the cache memory with the prefetched cache line from the prefetch buffer based on the number of accesses to the replacement candidate line.

Abstract: An apparatus is disclosed for deterministically performing active-active failover of redundant servers in response to a failure of a link on which each server provides a heartbeat to the other server. Each of the servers is configured to take over the identity of the other server on a common network in response to detecting a failure of the other server's link heartbeat. Each server provides a status indicator to a storage controller indicating whether the other server's link heartbeat stopped. The storage controller determines the link has failed if both of the status indicators indicate the other server's heartbeat stopped, and responsively kills one of the servers. The storage controller also receives a heartbeat directly from each server. If only one direct heartbeat stops when the status indicators indicate the link heartbeats stopped, then the storage controller detects one server has failed and inactivates the failed server.

Abstract: An apparatus for reducing data unavailability time after a loss of main power in a storage controller is described. The controller backs up its volatile memory containing posted-write data to a non-volatile memory upon detecting a loss of main power. The controller continues to provide battery power to the volatile memory to sustain the posted-write data. If the battery is able to supply power to the volatile memory until main power is restored, the controller foregoes restoring the posted-write data to the volatile memory from the non-volatile memory. By not incurring the restore time, which may be substantial if the volatile memory is large since read rates from volatile memories are typically slow, the data unavailability time is reduced. The selective restore feature is user-disableable and also includes a brown-out timer for allowing a user to specify how long to battery-power the volatile memory if the feature is enabled.

Abstract: An apparatus for performing an MultiMedia extension (MMX) Packed Sum of Absolute Differences (PSADBW) instruction is disclosed. The apparatus includes carry-generating subtraction logic that generates packed differences of the subtrahend from the minuend and associated carry bits indicating whether the difference is positive or negative. The apparatus selectively inverts the differences based on the carry bits. Addition logic adds the selectively inverted differences and carry bits substantially in parallel to generate the PSADBW instruction result. In one embodiment, the apparatus also includes two muxes. The first mux selects the selectively inverted differences in the case of a PSADBW instruction and selects a multiply instruction's partial products otherwise. The second mux selects the carry bits in the case of a PSADBW instruction and selects a second multiply instruction's partial products otherwise. The two mux outputs are provided to the addition logic.

Abstract: A bus bridge on a primary RAID controller receives user write data from a host and writes the data to its write cache and also broadcasts the data over a high speed link (e.g., PCI-Express) to a secondary RAID controller's bus bridge, which writes the data to its mirroring write cache. However, before writing the data, the second bus bridge automatically invalidates the cache buffers to which the data is to be written, which alleviates the primary controller's CPU from sending a message to the secondary controller's CPU to instruct it to invalidate the cache buffers. The secondary controller CPU programs its bus bridge at boot time with the base address of its mirrored write cache to enable it to detect that the cache buffer needs invalidating in response to the broadcast write, and with the base address of its directory that includes the cache buffer valid bits.

Abstract: An application server blade for an embedded storage appliance is disclosed. The blade includes a printed circuit board (PCB) with a connector for connecting to a chassis backplane including a local bus. Affixed on the PCB is a server, a portion of a storage controller, and an I/O link coupling the server and storage controller portion. The server transmits packets on the I/O link to the storage controller portion. The packets include commands to transfer data to a storage device controlled by the storage controller. The storage controller portion receives the packets from the server on the I/O link and forwards the commands on the backplane local bus to another portion of the storage controller affixed on a separate PCB also enclosed in the chassis. The blade also includes a removal mechanism for hot-replacement of the blade in the chassis. The blade architecture facilitates software reuse.

Abstract: A microprocessor that includes a random number generator (RNG) and an instruction for storing random data bytes generated by the generator. The RNG includes multiple buffers for buffering the random bytes and counters associated with each buffer for keeping a count of the number of bytes in each buffer. The instruction specifies a destination for the bytes to be stored to. In one embodiment, the number of bytes written to memory is variable and is the number of bytes available when the instruction is executed; in another, the instruction specifies the number. If variable, the instruction atomically stores a count specifying the number of valid bytes actually stored. In one embodiment the destination is a location in system memory. The count may be stored to memory with the bytes; or the count may be stored to a user-visible register. An x86 REP prefix may be used.

Abstract: A network storage appliance integrates a plurality of servers and a plurality of storage controllers into a single chassis. The storage controllers control transfers of data between the servers and storage devices controlled by the storage controllers. The servers and storage controllers comprise a plurality of field replaceable units (FRUs) that plug into a backplane also enclosed in the chassis. The FRUs are redundant such that any one of the FRUs may fail without incurring loss of availability of the data stored on the storage devices. One of the storage controllers detects a failure of one of the servers and responsively kills the failed server. The failure may be a stopped heartbeat from the failed server. Additionally, one of the storage controllers detects a failure of a heartbeat link coupling the servers and responsively inactivates one of the servers to enable failover to the live server.