Abstract: Structures and methods are described that inhibit atomic migration which otherwise creates an undesired capacitive-resistive effect arising from a relationship between a metallization layer and an insulator layer of a semiconductor structure. A layer of an inhibiting compound may be used to inhibit a net flow of atoms so as to maintain conductivity of the metallization layer and maintain the low dielectric constant of a suitable chosen insulator material. Such a layer of inhibiting compound continues to act even with the reduction of ground rules in succeeding generations of semiconductor processing technology. One embodiment includes an insulator having a first substance, wherein the first substance is selected from a group consisting of a polymer and an insulating oxide compound. The embodiment includes an inhibiting layer on the insulator, wherein the inhibiting layer includes a compound formed from a reaction that includes the first substance and a second substance.

Abstract: A video RAM (VRAM) includes a dynamic random access memory (DRAM) having a serial I/O port coupled to a pipelined serial access memory (SAM). The pipelined SAM operates by partitioning a serial read operation into a sensing operation, a counter operation, and an output operation, where all three operations are performed concurrently in a pipelined fashion. The VRAM performs a split read transfer (SRT) operation where data is serially read from one portion of the SAM while new data is transferred from the DRAM to a another portion of the SAM. The VRAM recognizes a late SRT operation occurring during the reading of the last bit from one of the SAM portions (known as a last bit transfer), when the address produced by a counter in the counter operation is one past a boundary of one of the SAM portions to invoke circuitry to automatically reload the counter and properly load the SAM pipeline.

Abstract: First and second flash memory cells or transistors, operating in the linear region of operation, are provided with different threshold values by providing different charges on their respective floating gates. The first of the pair of flash memory transistors is “over-erased” until it has a negative threshold voltage so that the first flash memory transistor is rendered permanently conducting when its control gate and source are at Vss. Circuitry is provided for connecting the first and second flash memory transistors in parallel circuits in which equal current values are generated in an equilibrium condition. Circuitry for sensing a voltage in each of the parallel circuits is provided to determine any imbalance in current values and provide an output voltage which may be used as an reference value when the currents are in equilibrium.

Abstract: An apparatus for determining the state of a multistate memory cell. The apparatus includes three sense amplifiers, each with an associated reference cell which produces a reference voltage for input to each of the sense amplifiers. The apparatus includes circuitry which allows the reference cell currents to be varied to produce the reference voltages or pairs of reference voltages needed to accurately determine the threshold voltage and hence state of a programmed or erased memory cell.

Abstract: Silicon-on-insulator (SOI) islands are formed in a silicon substrate. A first set of trenches is formed in the silicon substrate, leaving laterally-isolated rows of silicon between the trenches. The first set of trenches is then filled with silicon oxide. A second set of trenches is then formed in the silicon substrate at a direction orthogonal to the first set of trenches. Silicon nitride is then deposited over the sidewalls of the second set of trenches. An isotropic chemical etch is then used to fully undercut narrow the laterally-isolated rows of silicon between the second set of trenches to form evacuated regions beneath silicon islands. A subsequent oxidation step fills the evacuated regions to form the SOI islands.