Abstract: The invention provides a multiplexer structure having an efficient quadrilateral layout. The multiplexer structure includes a first multiplexer and a second multiplexer, both being coupled to receive a plurality of common input signals. Each multiplexer has a first stage and a second stage. The first stages of the first and second multiplexers are fabricated in a plurality of adjacent multiplexer stripes. Each multiplexer stripe includes a plurality of interleaved pass transistors. The multiplexer stripes are fabricated in parallel with each other along a first axis. Gate electrodes of the pass transistors extend in parallel with each other along a second axis that is perpendicular to the first axis. One or more rows of memory cells extend along the second axis, adjacent to the multiplexer stripes. These memory cells control the pass transistors in the multiplexer stripes.