Abstract: An encoder/decoder is described which allows data transmission on an A.C. coupled transmission system. The encoder converts a serial data stream comprised of combinations of logical "1"'s and "0"'s in an NRZ format to an output pulse train. The latter is characterized not only by phase reversal for each bit of data, as required for A.C. coupled systems, but by bit durations which are dissimilar for a logic "1" and "0". The encoded data is transmitted and subsequently applied to the decoder which restores the data to an NRZ format, and provides a corresponding series of clock pulses for interpreting the data. The encoder/decoder may be implemented in a simple logic configuration.

Abstract: A disposable electrostatic ink jet cartridge forms part of a printer head which is mounted to move transversely back and forth across the width of a recording paper. The cartridge includes an ink jet nozzle and multicompartment ink reservoir, one compartment supplying the ink jet nozzle with ink. As printing occurs, the head height of ink supplying the ink jet nozzle decreases. In order to restore proper height height, as the head moves in one direction, an external fixed cam engages a leaf spring connected to the cartridge, causing a connected float to displace ink contained in the other reservoir compartment. The displaced ink is forced over a dividing wall in the reservoir into the compartment on the front of which is mounted the ink jet nozzle. As the head reverses direction, the cam is disengaged from the leaf spring, thus restoring the float to a raised position.

Abstract: The apparatus is an improved web processor, which operates at a high web speed, and can achieve variable document lengths with only programmable changes. To achieve this result the web processor uses an improved tool and web drive control. The tool control insures that the tool contacts the web once per document length. The web drive control varies the web speed to mate with the tool during impact and then speed up or slows down the web to maintain a constant speed throughout the processing unit.

Abstract: A timed token protocol for use in a local area loop communications network is disclosed. The protocol provides three classes of service with a priority relationship between classes. The three classes allow guaranteed bandwidth, interactive and batch services. The classes are implemented by timing the rotation time of a write token to measure instantaneous load. Transmission of information is limited by class of service and the measured write token rotation time.Also disclosed is a hardware embodiment of a loop communications station which implements the timed token protocol.

Abstract: A memory mapping unit enables different sized memory boards to be mapped in any order into any size memory address boundary in a microprocessor. Any 2.sup.K sized memory board (where N.ltoreq.K.ltoreq.M) can be mapped to any 2.sup.N address boundary. To accomplish this, a binary adder adds the 2's complement of the base address register with significant bits from the address buss. A series of logic gates are connected to the output of the binary adder and a board size mask register. The logic gates perform an "AND" operation on the output from the binary adder and the board size mask register. The outputs from the logic gates connect to a multiple input "NOR" gate. When all the inputs are logical "zero", indicating the address is on the board, a board enable command is produced which activates the memory board transceiver.

Abstract: A large area button in an electrical keyboard is prevented from jamming by being stabilized against tilt which results from depressive forces being applied remotely from the center of the button, the stabilization being achieved by the provision of two anti-roll bars attaching the button to the body of the keyboard and each preventing deviation of one of two axes of the button from being orthogonal both to one another and to the direction of depression of the button.

Abstract: An electronic recognition circuit is described for use in bar code reader systems having postal and commercial applications. Such systems may be required to read codes which are of relatively poor print quality. The present circuit utilizes statistical auto-correlation techniques to reject extraneous ink dots and minor print voids commonly associated with such printing. Additionally, the circuit is skew tolerant and both position and velocity independent of the bar code being processed.

Abstract: The invention is a multipart continuous form having several plies and a means to securely fasten the plies which prevents longitudinal slippage. To achieve this result the form has a series of locking and connecting tabs cut along its edge. The locking tabs fasten the inner plies of the form to the connecting tab, thereby preventing longitudinal shifting.

Abstract: An apparatus is provided, for use in an impact printer, in which printer it is required that an impact producing hammer, or assembly of such hammers, be operable in more than one location, whereby the hammer or assembly of hammers is moved between operational positions, the operation of the hammer or assembly of hammers is inhibited except when correctly positioned for operation, any mispositioning of the hammer or assembly of hammers is automatically corrected, wear, introduced by movement of the hammer or assembly of hammers, is minimized, and high operational speed, of the printer, is attained.

Abstract: The invention is a defect tolerant memory for a computer system. The defect tolerant memory has a main memory, a redundant memory and a mask memory. The redundant memory receives and stores data redundant to that addressed to defective cells in the main memory. The redundant memory has multiple memory levels and uses a randomness technique to store redundant data for all chips of the main memory. The mask memory stores the location of each defect of main memory and indicates when a defective word is addressed in main memory. The mask memory is made up of multiple bit mask memories each cooperating with one of the redundant memory levels. Each bit-mask memory has multiple sub-memory units which use a randomness technique to store the addresses of defects in main memory.

Abstract: The present disclosure describes an hermetically sealed integrated circuit package capable of accommodating high density circuit configurations with their attendant high power levels. In performing this function, the package permits the back-bonded integrated circuit chip or die to be mounted to a thermally conductive member of the package which is disposed in an open air stream. Moreover, the opposite side of the package positioned in proximity to the interconnection medium remains available to be fully populated by a large number of closely spaced input/output pins.

Abstract: The present disclosure describes a dressing finger assembly of advanced design for use on automatic wiring machines. Such machines make solderless wrapped electrical connections on pluralities of planar disposed terminals. A dressing finger is employed to form predetermined wire patterns in conjunction with a wrap tool which makes the actual connection. It has been observed that the design of dressing fingers used in present day machines is such that the insulation of the wire being wrapped may be pinched and cut, thereby necessitating its replacement to avoid electrical shorting. In accordance with the present invention, the assembly comprised of a newly designed finger and supporting guide, provide the required retention and support of the wire during wrapping while eliminating the aforementioned damage to the wire.

Abstract: An electronic circuit is described for providing a low current DC supply at increased voltage with high efficiency and minimal hardware complexity. In performing its function, the circuit preferably utilizes a plurality of CMOS voltage-controlled solid state switches in conjunction with a sequenced clock pulse train to implement a compact capacitive-type multiplier. Thus, capacitors are charged in a predetermined order and the charges stacked upon one another to ultimately charge an output storage capacitor to a voltage level which is substantially a desired multiple of the supply voltage applied to the circuit. For descriptive purposes, the present inventive techniques are applied herein to the design for an octupler.

Abstract: An error detecting unambiguous multi-segmented indicia display method and apparatus is disclosed wherein an "OFF" segment is illuminated differently than an "ON" segment of the display to verify that the "OFF" segment is indeed "OFF" and not a malfunctioning "ON" segment. In the preferred embodiment a pulsating voltage is supplied to the "OFF" segments to provide a lower integrated average voltage and therefore a lower brilliance of display. In an alternate embodiment a contiguous "OFF" segment of one color is provided next to each "ON" segment so as to indicate unambiguously that each non-illuminated "ON" segment is in fact indicating "OFF".

Abstract: The present disclosure describes a multi-layered integrated circuit package especially suited for high density circuit applications, such as those involving LSI or ULSI. The package is characterized by short uninterrupted electrical circuit paths between the integrated circuit chip and an interconnection medium. The use of metallized vias or feed-throughs commonly employed in multi-layered packages have been eliminated. Also, heat dissipation is enhanced by the short thermal path between the chip and the outer package surface. Finally, the signal lead configuration permits the area occupied by the package on the interconnection medium to be significantly less than that of present-day packages having approximately the same number of input/output pins or terminals.

Abstract: An N phase digital inverter for converting an input DC voltage level to an output DC voltage level interposes between the input and output terminals thereof a plurality of N parallel switching circuits, each switching circuit thereof comprising in series a power switch and a transformer. The output of each transformer is coupled through a diode to a common point for filtering to generate the output DC voltage. The output DC voltage is sensed and fed to a logic generator for generating a ring sequence of pulses which activate sequentially each power switch in the plurality thereof. The logic generator controls the ratio of pulse time ON divided by pulse time ON plus pulse time OFF to maintain a desired level of output DC voltage.

Abstract: The present disclosure describes a side-loading wire wrapping assembly comprised of a specially configured bit and sleeve, for use on semi-automatic wiring machines. Such machines are used to make solderless wrapped connections on terminals emanating from a common plane. The wire wrapping assembly in present use on many of such machines consists of a fixed sleeve substantially enclosing a spring-loaded bit. The arrangement necessitates front-loading of the bit by the operator--a procedure which is tedious and time consuming. The present invention obviates these difficulties by converting the fixed-sleeve assembly from front-loading to side-loading. This is accomplished by providing in the sleeve, a wire feed aperture in contiguity with a longitudinal slot and of orienting the former with a widened portion of the slit formed in the bit periphery by the wire receiving bore.

Abstract: In a named data processing system, user ownership and verfication of data records is secured by assigning an unique record name to each data record, providing error checking covering both the data record and its associated record name, storing the data record, its associated record name and check code, and requiring the data record name to be provided in order to initiate a fetch operation. Further, the check code enables upon fetching, a verification that an incorrect data record was not inadvertantly fetched due to hardware or other failures. The association of a unique data name with each data record provides for self-descriptive data records thereby permitting the reconstruction of directories which describe the contents of various actual physical locations within an Input/Output system when such directions are lost or otherwise corrupted by hardware or other malfunctions.

Abstract: In a large parallel processing environment including a plurality of active registers storing either normalized floating point or integer data a high/low register selection circuit identifies selectively the register or registers storing either the highest or lowest numerical data value. The numerical data in each active register is first converted into a pure binary magnitude pattern having the same relative value as the original numerical data for a select high register search, and the inverse relative value for a select low register search. Thereafter, the binary patterns from all active registers are processed together two bits at a time through an OR network with the OR network output functioning to deactivate all registers having an OR'ed two bit pattern less than the OR network output value. The deactivating process is continued two bits at a time until either only one register remains active or all bits have been processed two bits at a time through the OR network.

Abstract: A method of data communications for use in systems employing serial transmission techniques in a ring or loop configuration. Access to the communication network is via a communications processor and a interface unit termed a node. The communications processor is responsible for network protocol and activities as well as for interfacing devices to the network. The node provides the only connection to the loop and drives the clock for the communications processor as well as the node itself from the transmitted data. All information in the communication network is transmitted in a modified Mauchly format and will appear as n-bit data or control characters. A binary ONE is represented as a signal level transition from one level to another, while a binary ZERO is represented by an opposite signal transition. A control character, which always precedes a data character, will either be the address of a node or a null.