Patents Represented by Attorney, Agent or Law Firm E. Russell Tarleton
  • Patent number: 6199495
    Abstract: A method and apparatus for sewing and cutting layered cloth wherein a sewing guide formed of at least semi-rigid, compliant material is used to guide the stitching of parallel lines to create channels within which the sewing guide is placed to act as a cutting mat when cutting the layers of fabric above the sewing guide, such as with a rotary cutting tool.
    Type: Grant
    Filed: May 18, 1999
    Date of Patent: March 13, 2001
    Inventor: Margaret D. Schafer
  • Patent number: 6198675
    Abstract: A circuit and method for replacing a defective memory line with a usable memory line. A test is carried out to locate any defective lines, whether a row line or a column line, within a block of memory. If a defective line is found, the identity of the defective line is stored in software code. The software code is stored in a file or table, or other acceptable location, together with the identification of the memory block which is associated with the test data. When the computer is enabled for operation, the test data is loaded from the file into a register associated with the memory. When the memory is addressed, the register prevents addressing to the defective memory line and replaces it instead with an alternative line in the memory which has been tested as usable for storing and retrieving data.
    Type: Grant
    Filed: December 23, 1998
    Date of Patent: March 6, 2001
    Assignee: Cray Inc.
    Inventors: Steven V. R. Hellriegel, Andrew S. Kopser, Robert R. Henry
  • Patent number: 6195290
    Abstract: A method of avoiding disturbance during the step of programming and erasing an electrically programmable, semiconductor integrated non-volatile memory device which includes a matrix of memory cells divided into sectors and programmable in a byte mode is disclosed. An operation of verification of the contents of the byte to be programmed, to be carried out for each individual bit, is provided even before the first program pulse is applied. The method also provides for the parallel erasing of several sectors during an erase step, and a verification of the erase step for each sector in the matrix. If the verification shows that a sector has been erased, the sector is applied no further erase pulses.
    Type: Grant
    Filed: September 27, 1999
    Date of Patent: February 27, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventors: Marco Dallabora, Corrado Villa, Simone Bartoli, Marco Defendi
  • Patent number: 6194948
    Abstract: A method, and related circuit, prevent the triggering of a parasitic transistor in an output stage of an electronic circuit. The stage includes a transistor pair with at least one transistor of the pull-up PMOS type having respective source, gate and drain terminals and a body terminal, and a parasitic bipolar transistor having a terminal connected to the body terminal. The method includes the steps of providing a capacitor connected between the body and source terminals of the PMOS transistor; and using a control circuit to suppress the body effect of the pull-up PMOS transistor.
    Type: Grant
    Filed: June 29, 1998
    Date of Patent: February 27, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventors: Enrico Scian, Fabrizio Martignoni, Riccardo Depetro
  • Patent number: 6186964
    Abstract: A hydro-massage pillow assembly (10) including a pillow assembly (12) in combination with a water source (18) and a control assembly (14) for use with spa tubs (16) and the like. The pillow assembly (12) includes interchangeable membrane assemblies (44, 46), that are made of material with different permeability. The cushioned, flexible pillow (34) conforms to the shape of the tub (16) to enhance appearance and comfort. A remote control head (26) permits users to conveniently control the temperature, pressure, and other desired control parameters of the massaging effect produced by the pressurized water in the pillow assembly (12).
    Type: Grant
    Filed: September 26, 1997
    Date of Patent: February 13, 2001
    Inventor: Tony J. Branham
  • Patent number: 6184051
    Abstract: A movable mass forming a seismic mass is formed starting from an epitaxial layer and is covered by a weighting region of tungsten which has high density. To manufacture the mass, buried conductive regions are formed in the substrate. Then, at the same time, a sacrificial region is formed in the zone where the movable mass is to be formed and oxide insulating regions are formed on the buried conductive regions so as to partially cover them. An epitaxial layer is then grown, using a nucleus region. A tungsten layer is deposited and defined and, using a silicon carbide layer as mask, the suspended structure is defined. Finally, the sacrificial region is removed, forming an air gap.
    Type: Grant
    Filed: January 7, 2000
    Date of Patent: February 6, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventors: Paolo Ferrari, Benedetto Vigna
  • Patent number: 6181602
    Abstract: A method for reading memory cells that includes supplying simultaneously two memory cells, both storing a respective unknown charge condition; generating two electrical quantities, each correlated to a respective charge condition of the respective memory cell; comparing the two electrical quantities with each other; and generating a two-bit signal on the basis of the result of the comparison. A reading circuit includes a two-input comparator having two branches in parallel, each branch being connected to a respective memory cell by a current/voltage converter. Both the two-input comparator and the current/voltage converter comprise low threshold transistors.
    Type: Grant
    Filed: May 28, 1999
    Date of Patent: January 30, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventors: Giovanni Campardo, Rino Micheloni, Alfonso Maurelli
  • Patent number: 6172913
    Abstract: A method for fast programming by tunnel effect a floating gate memory cell having a floating gate region separated from a substrate region by a gate oxide layer, wherein an electric field of at least 10 MV/cm is applied to the gate oxide layer for a programming time less than or equal to 100 ns, for example in the range between 20 and 100 ns, and in one embodiment preferably of approximately 50 ns. The gate oxide layer is preferably less than 10 nm. With the foregoing, floating gate memory cells operating as single level or multilevel RAM cells, of a static or dynamic type, or as flash or EEPROM cells, can be obtained where the programming time is substantially reduced.
    Type: Grant
    Filed: June 25, 1999
    Date of Patent: January 9, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventor: Bruno Ricc{grave over (o)}
  • Patent number: 6169691
    Abstract: A method for restoring the charge lost from memory cells, such as to restore the original voltage levels, within a time equivalent to the retention time. The condition of the memory cell is determined, for example, when the memory is switched on, or based on the time elapsed since the previous programming/restoration, or based on the difference between the present threshold voltage of the reference cells and the original threshold voltage of the (suitably stored) reference cells, or when predetermined operating conditions occur. This makes it possible to prolong the life of nonvolatile memories, in particular of multilevel type, wherein the retention time decreases as the number of levels (bits/cell) is increased.
    Type: Grant
    Filed: September 15, 1999
    Date of Patent: January 2, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventors: Marco Pasotti, Frank Lhermet, Pier Luigi Rolandi
  • Patent number: 4833815
    Abstract: A shellfish lure (10) is formed of a bait hook (12), nests (18) of entangled loops (20), and a weight (22) attached to a main line (24). The loops (20) are formed of individual strands (30) of resilient, flexible monofilament line bound together at a common point by a crimp (32) to ensnare crabs (38) or other shellfish attracted to the bait.
    Type: Grant
    Filed: April 29, 1988
    Date of Patent: May 30, 1989
    Inventor: Frederic R. Kershaw