Abstract: Apparatus and methods enabling the efficient and repeatable measurement of mobility performance of wireless data communications equipment are described. This is particularly useful for testing the impact of roaming of Wireless Local Area Network (WLAN) devices, such as clients, between their counterparts, such as access points. The apparatus and methods include controlled emulation of roaming by WLAN devices, using a set of WLAN tester units, by activating and deactivating instances of emulated devices on different tester units to simulate the physical translation of the actual WLAN devices in an environment. Simulation of increasing and decreasing distance during the roaming process is also rendered possible. This enables various mobility performance measurements to be made on WLAN devices in a repeatable manner, free from artifacts due to device manufacturing tolerances.

Abstract: This invention pertains to a multi-function tool that when assembled in different configurations would meet many needs of the home or commercial mechanic. One configuration is height adjustable allowing users to work safely in an elevated position over the engine compartment of a light truck (i.e. half-ton to one-ton vehicle) even if that vehicle is lifted or taller than factory normal. Another configuration is an engine stand to hold a small engine block so the mechanic may repair it. Yet another configuration is a crane or hoist to assist in lifting engines or parts of engines (e.g. heads) out of the engine compartment to prevent injury to the mechanic. This hoist could also aid in lifting the engine or engine parts onto the engine stand or onto another conveyance (i.e. onto a truck).

Abstract: A low power matchline sensing scheme where power is distributed according to the number of mismatching bits occurring on a matchline is disclosed. In particular, match decisions involving a larger number of mismatched bits consume less power compared to match decisions having a lesser number of mismatched bits. The low power matchline sensing scheme is based upon a precharge-to-miss sensing architecture, and includes a current control circuit coupled to each matchline of the content addressable memory array for monitoring the voltage level of the matchline during a search operation. The current control circuit provides a voltage control signal to the current source of the matchline to adjust the amount of current applied to the matchline in response to the voltage of the matchline. In other words, matchlines that are slow to reach the match threshold voltage due to the presence of one or more mismatching bits will receive less current than matchlines having no mismatching bits.

Abstract: A method and system are provided for maintaining a virtual ground node of an SRAM memory array at a minimum level sufficient for maintaining data retention. A circuit can maintain the virtual ground node at a virtual ground reference voltage of Vdd?(1.5*Vth), or maintain 1.5*Vth across the memory cells, where Vth is a threshold voltage of an SRAM memory cell transistor and VDD is a positive supply voltage. By tracking the Vth of the memory cell transistors in the SRAM array, the circuit reduces leakage current while maintaining data integrity. A threshold voltage reference circuit can include one or more memory cell transistors (in parallel), or a specially wired memory cell to track the memory cell transistor threshold voltage. The value of the virtual ground reference voltage can be based on a ratio of feedback chain elements in a multiplier circuit.

Abstract: A delay locked loop (DLL) is added to the system in order to provide an accurate, PVT insensitive translation of the drive clocks into the write data eye. Adding a master-slave DLL to the system provides an accurate, PVT insensitive translation of the echo clocks into the read data eye. Solidifying the timing critical drive and receive logic which directly interfaces to the I/O buffers reduces the pin-to-pin skews. Utilizing clock phase outputs of the DLL in the solidified drive and receive logic blocks reduces further the skew between the clock and related data signals, and also removes the reliance on a differential clock. The system allows a much more relaxed constraint on clock duty cycle. Design of circuitry within the solidified drive and receive logic blocks permits simple logic modeling for fit within an ASIC flow. Physical design of the solidified drive and receive logic blocks permits simple fit within ASIC place and route flows for increased ease of implementation and ease of reuse.

Abstract: A method and apparatus for removing fluid from a container using a conventional shaped charge such as those used in well perforation; the charge being spaced from the container wall, and producing an explosive jet, the explosive jet directed by a diffuser disk to provide a vent or drain.

Abstract: A CMOS automatic gain control (AGC) circuit that receives an analog control voltage and generates a temperature compensated gain voltage to linearly control the gain of a variable gain circuit operating in the sub-threshold region. A PTAT circuit having a resistor network coupled to a current mirror circuit operating in the sub-threshold region establishes a current having an proportional relationship to temperature. This current is used as a supply for a voltage to voltage converter circuit which generates an intermediate voltage in response to the analog control voltage. A linearizing circuit operating in the sub-threshold region pre-conditions the intermediate voltage, which is then applied to a variable gain circuit. The variable gain circuit is operated in the sub-threshold region, and the preconditioned intermediate voltage will control the amount of gain to be substantially linear with respect to the analog control voltage, and with a range of about 85 dB.

Abstract: Phase-locked loop circuitry includes charge pump circuitry, loop filter circuitry, and drag current circuitry. The charge pump circuitry generates a charge pump current based on a phase of an input signal. The loop filter circuitry receives the charge pump current. The drag current circuitry generates a drag current to draw charge in the opposite direction from the charging current from a loop filter integration capacitor in the loop filter circuitry that does not include voltage sensing circuitry.