Abstract: An apparatus and method for decreasing the amount of time necessary to load configuration data into Field Programmable Gate Arrays (FPGAs) or other integrated circuit devices. In a preferred embodiment, serially arrayed FPGAs receive a concatenated stream of data from a common data bus. As a first FPGA reaches a loading-complete state, an enabling token is passed from the first FPGA to an enabling input on the next FPGA. The process repeats until all devices are completely loaded or fully configured.
Type:
Grant
Filed:
May 13, 1997
Date of Patent:
November 17, 1998
Assignee:
Xilinx, Inc.
Inventors:
Charles R. Erickson, Lawrence Cy-Wei Hung