Abstract: A cable assembly is provided including an encapsulated cable having one or more elements and an intermediary section. The encapsulated cable extends along a length direction. The intermediary section extends along the length direction and is attached along a length of the encapsulated cable and extends outwardly therefrom. The intermediary section is configured to receive one or more fasteners for securing the cable assembly to an external surface without the one or more fasteners contacting the one or more elements.

Abstract: A method and system for remotely and automatically selecting and activating a profile of a telephone. In particular, a user defines telephone profile activation information and communicates this information to the telephone to activate a desired profile during a certain event. In a preferred embodiment, the present invention includes a calendar application whereby the user may input scheduling information and profile associations so that calendar information and profile associations are transmitted by the calendar application to the telephone and activated upon occurrence and for the duration of an event. In an alternate embodiment, the method of the present invention includes having the telephone update the calendar application. The preset invention is capable of working in different time zones by converting the calendar information into the current time zone of the telephone.

Abstract: The present invention is embodied in a system and method for creating markers on scroll bars of a graphical user interface. Basically, the present invention allows users to reference locations of interest within a document using scroll bars of a user interface by creating graphical halt and pause points on the scroll bar at the locations of interest. In general, the present invention includes a user interface with a digital document of an application being used by a user. The application has at least a vertical scroll bar for moving from one location to another within the digital document. The scroll bar includes a scroll box, stub points and end points. The stub points represent reference points within the digital document that are predefined by the user. The stub points either stop or pause the movement of the scroll box as it moves along the scroll bar. The end points represent the top and bottom portion of the digital document.

Abstract: The present invention includes as one embodiment a method for automatically controlling access to a mobile computing device with pertinent data. The method includes predefining access parameters of the mobile computing device, determining an actual location of the mobile computing device and using the actual location of the mobile computing device to automatically control access to the mobile computing device based on the predefined access parameters. Also, the method includes storing the predefined access parameters in a private Internet networked location, accessing and updating the predefined access parameters and sending the updated access parameters to the mobile computing device.

Abstract: A method for testing a computer bus using a bridge chip having a freeze-on-error option that enables a computer system's central processing unit (CPU) to recover and continue processing even when the computer bus is not functional. The testing method of the present invention remains transparent to a user and can be accomplished while performing standard diagnostics tests. In general, the present invention injects an input/output (I/O) error into a specific bus slot of the computer bus to test the functionality (such as the error recovery capability) of the bus. The present invention then recovers from the failure condition without having the computer system shutdown or stop working and without having to restart the computer system. More specifically, the method for testing a computer bus according to the present invention includes enabling the freeze-on-error option on the bridge chip, injecting an error into the specified computer bus slot and recovering from the injected error.

Abstract: A method and system for providing and dynamically managing the size of a storage space containing data structures depending on a current network load. The present invention expands the size of a storage space when the amount of data therein is large, thereby reducing the time spent searching for values within the data structure. When the amount of data within the storage space is small, the present invention contracts the size of the storage space to reduce the memory needed to maintain the storage space. In this manner, the present invention dynamically adjusts the size of the storage space in response to changing network loads to ensure that network performance remains optimized.

Abstract: A method and implementing computer system is provided for the creation of large numbers of threads in a computer system. An exemplary embodiment supports up to sixteen segments in memory of thread private data for each process or application program running on the system. Each segment contains support for 2K threads. These segments are identified in process' user structure which is located in the process private data segment of memory allowing cleanup collection on a per-segment basis. The thread's private data is composed of two parts, viz. its private kernel thread stack (96K) and uthread data structure. The uthread contains the individual data fields that are referenced only by the thread, including the register save area for the thread.

Abstract: The system and method of the present invention is embodied in a multi-state on-chip logic analyzer that is preferably integrated into a VLSI circuit. In general, the logic analyzer is preferably coupled to a multilevel trace array for storing event trace data generated by the logic analyzer. Input and output logic coupled to both the trace array and the logic analyzer allows reading or writing from or to the trace array, and programming of trigger and condition criteria for transitioning states within the logic analyzer. The logic analyzer has the capability match one or more programmable trigger events to satisfy one or more programmable conditions. Further, the logic analyzer preferably has the capability to initialize programmable conditions in desired states, and to store event trace data in an on-chip array for trace data reconstruction and analysis.

Abstract: The present invention is embodied in a system and method for projecting a liquid crystal display (LCD) of a personal data assistant or mobile telephone. In general, the present invention enables users of PDAs and/or mobile telephones to enlarge the view of textual and graphical images. Namely, the present invention is embodied in a system and method that projects the LCD display screen of LCD displaying devices, such as PDAs and/or mobile telephones, onto a larger surface, for example, the back of car or airplane seat. This allows Internet information, including World Wide Web (WWW) pages or online demos with text and images to be enlarged. Also, enlargement of text and images by the projection arrangement of the present invention allows easier reading for people that have difficulty seeing small text/numerical characters and images.

Abstract: A no-integrity management method and system for managing logical volumes of a computer system. The no-integrity refers to the fact that the availability status of each partition within the mirrored logical volumes is not written to a direct access storage device but instead stored within a volatile memory. When the computer system is shutdown the availability status information is discarded, and the availability status of each partition is marked as active upon first open of a partition after startup of the computer system.

Abstract: The present invention is embodied in a system and method for predicting design errors, such as errors in integrated circuit design. The system and method of the present invention use a probabilistic model, such as a Bayesian Belief Network (BBN), to predict design errors at any point in the design process by using information about the current design in combination with historical design error data from previous designs. Prediction of design errors is based on a probabilistic comparison of conditions or error symptoms in the current design, to similar or identical conditions or error symptoms associated with design errors identified in prior designs.

Abstract: The present invention is embodied in a system and method for sharing input and output pins between a plurality of separate logic circuits coexisting within a single microprocessor such that the microprocessor is capable of assuming the characteristics of a desired logic circuit. The present invention achieves controlled sharing of bidirectional input and output pins without the requirement to use multiplexing logic. Because the pins may be shared among a plurality of logic circuits, a single microchip may be used for completely different purposes by enabling or disabling selected logic circuits. In other words, a single microchip can take on any number of properties by simply enabling one or more logic circuits while disabling other.

Abstract: The present invention is embodied in a system and method for recovering from design errors, such as errors in an integrated circuit design. The system and method of the present invention use a probabilistic model, such as a Bayesian Belief Network (BBN), in combination with case-based inferential reasoning to predict or detect design errors at any point in the design process by using information about the current design in combination with historical design error data from previous designs. Once conditions associated with design errors are predicted or detected, an error profile is generated. An inference engine then uses conditional probabilities produced by the probabilistic model to compile a set of exact or similar cases from a historical knowledge base containing solutions and workarounds to previously identified design errors, based on their probable relevancy to the current design case.

Abstract: An enhanced probe apparatus is provided for facilitating pin contact on a multi-pin integrated circuit or other high density connector-pin environment. The probe includes, in one exemplary embodiment, a magnification lens and an LED lamp which are both are mounted in various arrangements to an oscilloscope probe device. Both the lens and the LED are adjustable independently and each is movable in a plurality of directions to optimize the magnification and illumination of a pin contact area on one edge of an integrated circuit chip in order to facilitate pin identification and probe-to-pin contact for signal acquisition.

Abstract: A method and implementing system are provided in which processor registers are divided into sectors and such sectors are individually renamed. In one embodiment, the register file is divided into sectors such that the smallest accessible unit for an instruction set in each register can be uniquely addressed and renamed thereby providing additional effective registers for renaming.

Abstract: A method and system for dividing computer processor registers into sectors and storing frequently used data in the most significant unused sectors. The method includes sector renaming that is performed on each individual sector (i.e., on a sector-by-sector basis) rather than renaming an entire processor register. A register is divided into sectors such that the smallest accessible unit for an instruction in each register can be uniquely addressed and renamed. A register file is divided into sectors so that each process register can be uniquely addressed and renamed. The most significant sectors of the processor registers are used to hold pre-assigned values therein. Data previously loaded into processor register sectors is stored in the most significant sectors of the processor registers for possible future referencing and use. The method also includes establishing a sign-extend memory that includes at least one sign-extend bit in a sector status table.

Abstract: The present invention is embodied in a clock controller for generating and controlling the phase alignment of a plurality of ratioed sub-clocks. A master clock is preferably input to a clock splitter to provide a plurality of slave clocks. Phase holds, generated from the slave clocks, are then used to gate each of the slave clocks to produce ratioed clocks that produce phase aligned clock pulses at integer factors of the master clock frequency. The clock controller controls the ratioed clocks by processing commands to start, stop, or pulse the ratioed clocks.

Abstract: The present invention is embodied in a system and method for fast computation of a spatial transform of an input signal. The computation system includes a window processor having a window function and an operator having a first set of weights. The window processor receives the input signal as sample blocks and the operator is adapted to apply butterfly coefficients determined by the window function to produce resulting vectors. Also, the window processor maps the input signal to a cascade of butterflies using the first set of weights and reorders the cascade of butterflies. A transform processor having a transform module computes a spatial transform from the reordered cascade of butterflies to produce transform coefficient. A coefficient combination operator combines the transform coefficients to produce an encoded output corresponding to the input signal.

Abstract: An improved flexible cable construction is provided which includes two layers of conductor traces arranged alternately with three layers of dielectric material in a flattened configuration between ground plane outside metal surfaces. Each of the conductor layers includes alternating signal traces and ground traces. In an exemplary embodiment, vias are arranged in first and second planes through the cable. Longitudinal vias maintain the potential of ground planes at the same level as well as improving shielding effectiveness along an edge or thickness cross-section of the cable. Transverse vias are implemented to minimize antenna effects due to large openings at the point of cable entry into a sheet metal box containing high frequency electronics.

Abstract: The coder/decoder (codec) system of the present invention includes a coder and a decoder. The coder includes a multi-resolution transform processor, such as a modulated lapped transform (MLT) transform processor, a weighting processor, a uniform quantizer, a masking threshold spectrum processor, an entropy encoder, and a communication device, such as a multiplexor (MUX) for multiplexing (combining) signals received from the above components for transmission over a single medium. The decoder comprises inverse components of the encoder, such as an inverse multi-resolution transform processor, an inverse weighting processor, an inverse uniform quantizer, an inverse masking threshold spectrum processor, an inverse entropy encoder, and an inverse MUX. With these components, the present invention is capable of performing resolution switching, spectral weighting, digital encoding, and parametric modeling.