Abstract: Improved EMI/RFI shielding is provided for situations which require heavy duty wiping insertions, such as occurring when a relatively heavy electronic assembly is to be removably inserted in a cabinet. In accordance with the invention, inexpensive integral EMI/RFI strips of conductive spring material are riveted to opposite cabinet walls so as to be adjacent the wiping sides of the inserted electronic assembly. Each EMI/RFI strip contains integral longitudinally spaced projecting fingers formed to provide durable and highly reliable EMI/RFI shielding capable of withstanding many insertions and removals.

Abstract: Apparatus for providing automatic clock de-skewing for a plurality of circuit boards of a data processing system. In a preferred embodiment, each circuit board is of multi-layer construction and contains a clock distribution chip which includes on-chip automatic clock de-skewing circuitry for providing de-skewed clocks to other chips on the circuit board. In a preferred implementation of the clock de-skewing circuitry, feedback circuitry including a multi-tapped delay line and an accurate reference delay are employed in conjunction with a phase comparator for automatically providing de-skewed clocks at the clock outputs of the clock distribution chip. The accurate reference delay is advantageously provided by a strip transmission line formed in a conductive layer of the multi-layer board containing the chips.

Abstract: A method of providing automatic clock de-skewing for integrated circuit chips carried by a multi-layer circuit board. In a preferred implementation of the method, a clock distribution chip includes on-chip automatic clock de-skewing circuitry requiring an accurate reference delay which is advantageously provided by a strip transmission line formed on one of the conductive planes of the multi-layer circuit board containing the chips.

Abstract: Error detecting and correcting operations for a plurality of input bits comprised of input data bits and associated check bits are implemented using two IC chips in order to overcome chip output limitations. The use of two identical IC chips for this purpose is made possible by employing a specially chosen inversely symmetrical Hamming code and by wiring the input data bits and the input check bits in an inverse manner with respect to the input terminals of the two IC chips. As a result, even though each IC chip performs the same error detecting and correcting operations, it does so inversely with respect to the input data bits and the input check bits so that each IC chip is able to provide one-half of the required output bits.

Abstract: A method employing two identical IC chips for providing error detecting and correcting operations on a plurality of input bits comprised of input data bits and input check bits, wherein a single one of the IC chips has an insufficient number of available outputs to provide all of the required outputs. The method includes applying the input data bits and the input check bits to the input terminals of each IC chip in an inverse manner relative to one another, and then performing the error detecting and correcting operations on each chip in accordance with an inversely symmetrical Hamming code. As a result, even though the same detecting and correcting operations are performed on each IC chip, they are performed in an inverse manner with respect to the input data and input check bits so that each IC chip is able to provide one-half of the required output bits.

Abstract: Error detecting and correcting operations for a plurality of input bits comprised of input data bits and associated check bits are implemented using two IC chips in order to overcome chip output limitations. In addition, redundancies derived from the use of two IC chips are employed to provide automatic self-checking of the detecting operation of each chip. The use of two identical IC chips for this purpose is made possible by employing a specially chosen inversely symmetrical Hamming code and by wiring the input data bits and the input check bits in an inverse manner with respect to the input terminals of the two IC chips. As a result, even though each IC chip performs the same error detecting and correcting operations, it does so inversely with respect to the input data bits and the input check bits so that each IC chip is able to provide one-half of the required output bits.

Abstract: Disclosed are reciprocating carriages carried on roll bearings engaged on guide rails, where some of the bearings are made flexible to be compliantly engaged against a rail surface.

Abstract: A method employing two identical IC chips for providing error detecting and correcting operations on a plurality of input bits comprised of input data bits and input check bits, wherein a single one of the IC chips has an insufficient number of available outputs to provide all of the required outputs. The method includes applying the input data bits and the input check bits to the input terminals of each IC chip in an inverse manner relative to one another, and then performing the error detecting and correcting operations on each chip in accordance with an inversely symmetrical Hamming code. In addition, by taking advantage of redundancies in the performance of error detecting operations, the method also provides for automatic self-checking of chip operations.

Abstract: A relatively large plurality of relatively small, independently operating disk subsystems are coupled to a read/write interface containing error circuitry and data organizer circuitry. The data organizer circuitry organizes read/write data for read/write communication with the disk subsystems via the error circuitry such that the overall system appears as a large, high capacity disk system having an unusually high fault tolerance and a very high bandpass.

Abstract: A method of recovering from an error condition during operation of a program that is modifying a data base without corrupting the data base, wherein the program includes calls to record the progress of the operation in a table in memory. On the occurrence of an error condition, the tables for all programs in operation are transferred to a disk. During error recovery, the tables are returned to memory where the information stored in the respective tables is used by each active program to restore operation of the particular program to a point where the operation can be completed without corrupting the data base. Each program is designed to interrogate its own recovery table following the occurrence of an error condition to restore operation at a point where the integrity of the data base is assured.

Abstract: Apparatus for precisely edge aligning and offsetting or jogging stacks of sheet items wherein two oppositely disposed alternately actuated continuously rotating paddle members each produce driving forces at right angles to one another effective to force each item first in one direction and then in another direction at right angles thereto such that the sheet items operational with respect to any paddle are caused to be stacked in offset alternating piles against confronting opposite walls of a stacker frame member.

Abstract: On-line timing signal fault detection is provided by taking advantage of differential signal distribution commonly employed in digital data processing systems. An acceptance window indicative of permissible phase shift variations between the differential signals is established using a plurality of flip-flops having clock and data inputs to which delayed, undelayed, inverted and uninverted versions of the differential signals are applied in a predetermined manner. Also included is the capability of providing fault detection even when one of the differential signals is lost.

Abstract: Arbitration apparatus provides first-come-first-served access for a plurality of requestors to a commonly shared unit, such as a memory. Each requestor is provided with a counter which is advanced each cycle from an initial count until its respective requestor is granted access. During each cycle, fast programmable array combinational selection logic operates in response to the counter outputs to select the requestor which has been waiting the longest. Tie-breaking combinational logic is additionally provided for resolving ties. The speed of operation of the combinational selection logic and the combinational tie-breaking logic is chosen so that requestors can be granted access at a rate of one per cycle.

Abstract: An optical storage system employing a laser beam which is directed and focused onto an optical disk for reading and/or writing data in a track of the disk. Positioning control is achieved by providing for track following and track seeking using a plurality of interactive servo-loops. Proper focusing is maintained using focusing control circuitry which produces a focus error signal that is applied to a focus motor. This focusing control circuitry is able to return the objective lens assembly to its in-focus position so long as the objective lens assembly remains within a predetermined capture range. In the event that the objective lens assembly is outside of this capture range, a waveform generator is enabled which produces a correction signal that causes the focus motor to move the objective lens assembly back within the capture range with a velocity and for a time period sufficient to permit the focusing control circuitry to regain control and return the objective lens assembly to its in-focus position.

Abstract: An optical storage system employing a laser beam which is directed and focused onto an optical disk for reading and/or writing data in a track of the disk. Proper focusing is maintained using focusing control circuitry which produces a focus error signal that is applied to a focus motor. This focusing control circuitry is able to return the objective lens assembly to its in-focus position so long as the objective lens assembly remains within a predetermined capture range. In the event that the objective lens assembly is outside of this capture range, a waveform generator is enabled which produces a correction signal that causes the focus motor to move the objective lens assembly back within the capture range with a velocity and for a time period sufficient to permit the focusing control circuitry to regain control and return the objective lens assembly to its in-focus position.

Abstract: Multi-phase subroutine control apparatus for use in a data processing system which provides for the concurrent execution of a plurality of tasks in a multiprogramming and multiprocessing environment. Subroutine control operations are staged so as to share common hardware in a manner which in effect provides a plurality of phased concurrently operating subroutine control circuits wherein each circuit provides control for a different one of a plurality of concurrently executing tasks. The common subroutine hardware includes a multi-level stack for each task and a fast access return address register which permits a return address to be rapidly made available when required during execution of a task.

Abstract: A method for automatically adjusting the propagation time delay of an electrical circuit, such as an integrated circuit chip. In a preferred embodiment, the method is employed to de-skew the clock outputs provided by a plurality of clock distribution chips having different signal propagation times. In a preferred implementation of the method, feedback circuitry including a multi-tapped delay line and an accurate constant delay are employed in conjunction with a phase comparator for automatically adjusting the propagation delay of each chip to provide substantially the same constant delay relative to a main system clock for the clock outputs provided by the clock distribution chips.

Abstract: Apparatus for automatically adjusting the propagation time delay of an electrical circuit, such as an integrated circuit chip. In a preferred embodiment, automatic de-skewing circuitry is provided on each of a plurality of clock distribution chips for de-skewing the clock outputs from different chips. In a preferred implementation of the de-skewing circuitry, feedback circuitry including a multi-tapped delay line and an accurate constant delay are employed in conjunction with a phase comparator for automatically adjusting the propagation delay of each chip to provide substantially the same constant delay relative to a main system clock for the clock outputs provided by the clock distribution chips.

Abstract: Focus detecting apparatus is disclosed which is useful, for example, in an optical storage system for detecting the quality of focusing of a laser beam on the surface of an optical medium. For focus detection purposes, the reflected beam is collected and separated into two beams which are applied to first and second photosensitive elements, respectively. Focus detection is achieved based on determining the difference between the diameters of the beams incident on the photosensitive elements which are located so that the diameters of the beams applied thereto are indicative of the quality of focusing of the beam on the surface.

Abstract: An optical storage system is disclosed having improved spatial combining and separating apparatus along with improved focus detection and control apparatus. The spatial combining and separating apparatus functions to precisely combine a writing laser beam with a reading beam prior to focusing on an optical medium, and also functions to separate the reading and writing beams after reflection from the medium in a manner so as to prevent interference therebetween. The improved focus detecting and control apparatus employs a portion of the reflected reading beam to derive two beams which are applied to first and second photosensitive elements, respectively. Focus detection is achieved based on determining the difference between the diameters of the beams incident on the photosensitive elements which are located so that the diameters of the beams applied thereto are indicative of the quality of focusing of the beam on the surface.