Patents Represented by Attorney Edward J. Feeney
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Patent number: 4031512Abstract: A data communication network system for interconnecting a group of heterogeneous computers, batch terminals and conversational terminals employing serial transmission techniques in a ring or loop configuration. Each computer or terminal is connected to the communication network via communications processor and a interface unit termed a node. The communications processor is responsible for network protocol and activities as well as for interfacing devices to the network. The node provides the only connection to the ring or loop and derives the clock for the communications processor as well as the node itself from the transmitted data. All information in the communication network is transmitted in a modified Mauchly format and will appear as n-bit data or control characters. A control character, which always precedes a data character, will either be the address of a node or a null. To read information from the network, the node must detect a control character which represents its address.Type: GrantFiled: May 29, 1975Date of Patent: June 21, 1977Assignee: Burroughs CorporationInventor: Ulbe Faber
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Patent number: 4025768Abstract: Improved methods and apparatus for testing and diagnosing defects in data processing networks and circuits. The presence of a time-dependent error in a network is determined by testing the network at normal and reduced clock frequencies. If a time-dependent error is found to be present, the clock period during which the error occurs is then determined by repeating the testing of the network at normal clock frequency a predetermined number of times with a different selected clock period being extended for each such repeated test operation. The amount of the clock period extension is chosen to be sufficiently long to prevent occurrence of a time-dependent error if it should occur during that clock period. The error clock period is then determined based on a determination of the particular repeated test operation for which the time-dependent error did not occur.Type: GrantFiled: May 24, 1976Date of Patent: May 24, 1977Assignee: Burroughs CorporationInventors: Michael Herodotus Missios, John Richard Werner
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Patent number: 4022370Abstract: Apparatus for removing and replacing dual in-line solid state circuit chip devices and/or receptacles or sockets from printed wiring or circuit (PC) boards comprising means for positioning a printed wiring board adjacent to a source of radiant energy capable of soldering and desoldering said devices, means for automatically, cyclically extracting a device from said board and replacing said device with another similar device, means forceably removing the excess solder residue retained by the board when the device is extracted, means for automatically timing both the device extraction and insertion and the soldering and desoldering operation, and means preventing device extraction should the desoldering operation fail to release the device from the PC board.Type: GrantFiled: April 30, 1976Date of Patent: May 10, 1977Assignee: Burroughs CorporationInventor: David John Durney
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Patent number: 4017965Abstract: In the manufacture of a transducer head, a plurality of elongated slots are formed in a non-magnetic substrate to receive magnetic cores having a transducing gap. A sealing composition bonds the cores in the slots and the cores are then laser trimmed to predetermined widths and at predetermined core-to-core spacings.Type: GrantFiled: June 16, 1975Date of Patent: April 19, 1977Assignee: Burroughs CorporationInventors: Werner Brutsch, Michael Isaac Behr, Ko Ko Gyi
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Patent number: 4016409Abstract: Longitudinal parity is continuously provided for a predetermined plurality of words stored in a digital memory in a simple and expeditious manner without interfering with normal memory operation. The outputs of the memory read and write registers are applied in corresponding bit pairs to respective ones of a plurality of Exclusive ORs whose outputs are employed to update the respective flip flops of a longitudinal parity register at a time which is specially chosen so that the old word read out of the memory and the new word to be written therein are simultaneously available in the read and write registers.Type: GrantFiled: March 1, 1976Date of Patent: April 5, 1977Assignee: Burroughs CorporationInventor: Dongsung Robert Kim
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Patent number: 4015764Abstract: The present invention relates to semi-automatic apparatus for aligning and inserting a solid state electrical circuit chip or solid state chip receiving socket assembly into a printed circuit board or panel and automatically clinching a portion of the leads thereof so as to retain the chip and/or socket against accidental dislodgement from the circuit board prior to dip or wave soldering of the board.Type: GrantFiled: May 30, 1975Date of Patent: April 5, 1977Assignee: Burroughs CorporationInventor: David John Durney
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Patent number: 4011439Abstract: A plurality of modular arrays, each structured from a common module, are connected together so as to form a binary quotient by successive approximations. For divisors that fall into that group of numbers that have reciprocals with a reasonably short period, the forming of a quotient with such a divisor and any dividend can be greatly accelerated after the add and shift sequence for the first period of the divisor reciprocal is obtained. A unity array, divisor array, dividend array, and quotient array may all be of equal length, but must be longer than the length of the periods of the reciprocals of the divisors utilized. The reciprocal of the divisor is effectively formed in the divisor array by generating a shift and add sequence that will produce a product that is a series of binary ones. After the first period of the divisor reciprocal is formed, the binary bits of the reciprocal start to repeat for the second period, and so on.Type: GrantFiled: December 15, 1975Date of Patent: March 8, 1977Assignee: Burroughs CorporationInventor: Walter Scott Bennett
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Patent number: 4009437Abstract: The present disclosure describes a device for checking the dc characteristics of electronic nets disposed for example in assemblies utilized in data processing equipment. The operation of the analyzer assumes the presence of one or more controlled impedance nets, as may be achieved through the use of current mode logic configurations. The device which is employed while the circuit under test is in a power-off condition, first determines which type of net is being tested, passes a current of known magnitude through the net, and then compares the actual voltage developed thereacross with expected voltage values falling within a tolerance range. The voltage corresponding to the nominal impedance of the net and the tester current passed therethrough, lies at the center of the range. The analyzer automatically checks all the pins of a monolithic integrated circuit chip in sequence. If the nets associated with all the pins fall within the tolerance ranges, a "good" indication occurs upon test completion.Type: GrantFiled: March 31, 1976Date of Patent: February 22, 1977Assignee: Burroughs CorporationInventor: William Arthur Lacher
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Patent number: 4001699Abstract: A circuit for controlling the height of a bar graph display in response to a digital input signal. A first count, representing the particular cathode segment of the bar graph under energization, is developed by a counter which monitors the clock signal driving the bar graph display. A second count is developed by a counter stepped by a clock when the digital input signal is in a selected logic state. At the end of a selected interval, the counters contents are transferred to a register for supply to a digital comparator, which compares the first and second counts and produces a control signal upon their equality.Type: GrantFiled: September 15, 1975Date of Patent: January 4, 1977Assignee: Burroughs CorporationInventors: William Michael Denny, Russell Louis Hagen, Steve Ka-Lai Leung
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Patent number: 4000045Abstract: A printed-circuit board requiring precious metal electroplating of its contact finger areas is adapted for such plating by a temporarily affixed electroplating current carrier of metallic foil held in contact with other printed wiring interconnected with the contact finger areas. The metallic foil is shielded from contact with electroplating baths by a strip of dielectric plastic film, the film and the foil being temporarily held in a selected position on the board by a layer of non-setting pressure-sensitive adhesive.Type: GrantFiled: November 21, 1975Date of Patent: December 28, 1976Assignee: Burroughs CorporationInventor: Richard Ralph Rotzow
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Patent number: 3987823Abstract: The present disclosure describes a wire guide for use with a manually operated wire wrap gun. Such guns are used to make solderless wrapped connections on terminals emanating from a circuit board. The wire guide of the present invention is especially useful with multi-spindle guns, such as the dual spindle gun utilized for simultaneously wrapping both wires of a twisted pair or miniature coaxial cable. The present wire guide which is fastened to the sleeve portion of the gun, permits the operator to front load the gun quickly and reliably by directing the multiple wires into the respective wire feed openings of the wrapping tool bits housed within the sleeves.Type: GrantFiled: November 28, 1975Date of Patent: October 26, 1976Assignee: Burroughs CorporationInventors: Samuel Richard Romania, George Joseph Sprenkle
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Patent number: 3983539Abstract: This disclosure relates to a programmable unit employing plural levels of sub-instruction sets in addition to conventional instruction sets. The conventional level of instruction sets is employed to specify computational routines and other processing algorithms to be carried out by the unit. Each instruction in a conventional set is implemented in the unit by a sequence of first level sub-instructions which specify the various operations to be carried out within the unit which operations are comprised within the specific routine. In turn, the various first level sub-instructions are implemented by second level sub-instructions which specify the various control signals required to set the various gates as required for the particular unit operation to be carried out. With this hierarchy of sub-instruction sets, first level sub-instruction sets may be interchanged dynamically during the operation of the unit to dynamically change the processing capability of the unit.Type: GrantFiled: July 10, 1975Date of Patent: September 28, 1976Assignee: Burroughs CorporationInventors: Ulbe Faber, Robert L. Davis, David A. Fisher, Joseph D. McGonagle
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Patent number: 3983324Abstract: The present disclosure describes semiconductor devices and circuits for sending and receiving data at high speed between computer modules with excellent noise immunity and low drive power. The semiconductor circuits are arranged to send data single-ended and to receive data differentially. As is required for full duplex operation over a pair of wires, the circuit arrangements are such that a driver in a given driver/receiver module does not influence the incoming data.Type: GrantFiled: March 31, 1975Date of Patent: September 28, 1976Assignee: Burroughs CorporationInventor: William Arthur Lacher
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Patent number: 3983541Abstract: This disclosure relates to a programmable unit employing plural levels of sub-instruction sets in addition to conventional instruction sets. The conventional level of instruction sets is employed to specify computational routines and other processing algorithms to be carried out by the unit. Each instruction in a conventional set is implemented in the unit by a sequence of first level sub-instructions which specify the various operations to be carried out within the unit which operations are comprised within the specific routine. In turn, the various first level sub-instructions are implemented by second level sub-instructions which specify the various control signals required to set the various gates as required for the particular unit operation to be carried out. With this hierarchy of sub-instruction sets, first level sub-instruction sets may be interchanged dynamically during the operation of the unit to dynamically change the processing capability of the unit.Type: GrantFiled: July 10, 1975Date of Patent: September 28, 1976Assignee: Burroughs CorporationInventors: Ulbe Faber, Robert L. Davis, David A. Fisher, Joseph D. McGonagle
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Patent number: 3980874Abstract: Modulo M translation is performed on a large binary number of n bits by grouping the binary number in contiguous sets of approximately K bits each, storing the modulo M residues for each K bit set in an individually associated pre-stored ROM, reading the modulo M residues for a particular K bit segment of a binary number out of the ROMs, and performing modulo M addition on the read-out residues. Thus, modulo M translation of a positive number is accomplished in n/k modulo M additions and a table look-up, with the look-up table being stored in n/k ROMs. A subsequent modulo M subtraction is performed if the binary number is negative.Type: GrantFiled: May 9, 1975Date of Patent: September 14, 1976Assignee: Burroughs CorporationInventor: Chandrakant R. Vora
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Patent number: 3971419Abstract: The present disclosure describes an improved dressing finger for use with automatic wiring machines. Such machines are used to make solderless wrapped connections on terminals emanating from a common plane. The dressing finger which is used to form predetermined wire patterns is associated with a wrap tool which makes the actual connection. In present day machines, the distance relationship between wrap tool and dressing finger is fixed in one axis and the terminal grid arrangement which is dependent thereon is likewise fixed. The dressing finger of the present invention permits a combination of grids or fixed grids within a predetermined range, thereby providing greater flexibility in the design of the terminal panel.Type: GrantFiled: July 31, 1975Date of Patent: July 27, 1976Assignee: Burroughs CorporationInventor: George J. Sprenkle
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Patent number: 3972024Abstract: An improved microinstruction memory addressing method and apparatus within a serial-bit microinstruction processor incorporating internal, serial-byte transfer, is provided by addition to and alteration of memory control circuitry wherein the resulting permissible microinstruction set for controlling the processor may be expanded to include a CALL, GO-TO and EXECUTE operations, thus increasing the programmatic capabilities in the processor. The micro-code needed to define more complicated program operations, and thus the time used to perform these operations, may therefore be greatly reduced. Changes may also be made in existing timing circuitry.Type: GrantFiled: March 27, 1974Date of Patent: July 27, 1976Assignee: Burroughs CorporationInventors: Franklin T. Schroeder, John P. McAllister
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Patent number: 3962562Abstract: A control for a resistance solder unit for maintaining solder probe temperature within an acceptable range is provided using a redundant interlocking switching circuit. A pair of dual, single pole, single throw, variable time delay electronic relays, and a pair of dual, single pole, single throw electrical relays may be interconnected into the supply line for the AC to DC soldering transformer to control the time and duration of current to a resistance soldering probe. Included may be an autotransformer-coupled feedback from the resistance solder ground return of the soldering probe. Typically, visual and audible signals provide probe power status.Type: GrantFiled: January 14, 1974Date of Patent: June 8, 1976Assignee: Burroughs CorporationInventors: William F. Carter, John H. Drinkard, Jr.
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Patent number: 3962611Abstract: The present disclosure describes electrical circuit means for providing an automatic power restart for unattended electrical equipment, such as computer cabinets, after an AC power failure and subsequent power restoration. The restart function is performed without interfering with the normal cabinet power sequencing during attended operation or maintenance. The circuit which utilizes a latch-in type relay to "remember" the last manually selected power control setting has general utility in new installations, as well as being adaptable to existing cabinet power systems.Type: GrantFiled: May 19, 1975Date of Patent: June 8, 1976Assignee: Burroughs CorporationInventor: Bruce Jeffrey Miller
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Patent number: 3960264Abstract: An item carrier for an item transport system wherein the carrier member is provided with means automatically adjustably movable as a result of the pendulum effect or tilt of the item effective to prevent accidental dislodgement or disengagement of the item from the carrier while simultaneously causing the tilt or pendulum movement thereof to continuously move the item into a tighter engaging position in the carrier with each tilt or swing.Type: GrantFiled: January 28, 1975Date of Patent: June 1, 1976Assignee: Burroughs CorporationInventors: Joseph C. Carbine, Robert S. Bradshaw