Abstract: A field desk apparatus, designed to be worn by a user, is configured with two soft triangular structures having a work platform as a common element. Shoulder straps and support straps form the remaining two elements for each of the soft triangular structures, respectively. The weight of a work piece, supported by the work platform, is distributed to a lateral belt of the field desk apparatus, via the soft triangular structures, to ergonomically balance the weight of the work piece about the user.

Abstract: A leadframe (10) architecture provides placement of multiple optocoupler pair devices (45, 50) in a minimum size footprint package. A detector flag (20) and LED flag (12) are placed on a common centerline (26) within the footprint. A critical length is determined for packaging factors lying along the centerline. The angle (28) formed between the centerline and the longitudinal axis (24) controls the optocoupler pair fit within the package. The angle (28) is calculated by taking the arc-sine function of the critical length divided by the footprint width.

Abstract: A novel off-line bootstrap startup circuit (10) including a high voltage device (100) for providing an initial bias voltage to an integrated circuit (IC) is provided. The high voltage device includes an NMOS transistor (102) having a high source to ground breakdown voltage thereby extending a bias voltage range provided to the IC. This bias voltage range may be needed to support large comparator (303) hysteresis and allow for an unregulated bias voltage. The bootstrap startup circuit becomes inoperative when the bias voltage exceeds a predetermined value.

Abstract: An electronic pressure sensor (10) is enhanced by attaching a sensor die (18) to a stress isolation platform (12) using an adhesive (42) having a similar thermal coefficient of expansion. The adhesive provides a hermetic seal between the stress isolation platform and the pressure sensor die. A via (20) in the stress isolation platform provides an opening for pressure to be applied to the sensor die. The stress isolation platform is attached to a plastic package body (16) via a semi-rigid adhesive (40) for providing stress isolation and a hermetic seal between the package body and the stress isolation platform. Any hostile chemical entering the via contacts an exposed diaphragm (50) of the sensor die to assert pressure against its piezoelectric network (52) to generate the electrical signals representative of the applied pressure but are kept away from the sensitive interconnects by the hermetic seals.

Abstract: A differential pressure sensor (10) has a sensor die (16) attached to a stress isolation package base (12) with a bonding glass (27) having a similar coefficient of thermal expansion. The bonding glass, and alternately an aluminum layer, provides a hermetic seal between the stress isolation base and sensor die. Pressure is applied to the sensor die port (24). A plastic housing (14) is attached to the stress isolation base with an adhesive (29). A port (23) in the plastic housing is filled with a silicone gel (22). A second pressure source is transferred by way of the silicone gel to the sensor die. Any hostile chemical entering the via contacts the first surface of the sensor die to assert pressure against a transducer circuit (25) to generate the electrical signals representative of the applied pressure but are isolated from the sensitive interconnects by the hermetic seal.

Abstract: A voltage level translator circuit converts an input signal referenced between first and second operating potentials to an output signal referenced between second and third operating potentials. The input signal is level shifted through cascoded transistors and latched by series inverters to drive upper cascoded transistors in the output stage. The input signal is delayed before driving lower cascoded transistors in the output stage. The output stage transistors are cascoded in a similar manner as the level shifting section. The logic state of the input signal determines whether the upper cascoded transistors or the lower cascoded transistors in the output stage are activated to set the logic state of the output signal of the voltage level translator circuit. Additional cascoded transistors may be stacked to extend the range of voltage translation. The voltage level translator circuit is applicable to sub-micron technology.

Abstract: A novel RS latch for use in asynchronous designs has been provided. The RS latch is made scannable by the use of additional circuitry which provides a basis for a scan chain signal to propagate in and out the scannable RS latch. Such a scannable RS latch greatly facilitates the testing of the asynchronous design.