Abstract: An averaging detector having a first transistor having a first resistor connected across the base and emitter, a first capacitor connected in a signal input line and to the base of a second transistor, the collectors of the first and second transistors being connected to a positive voltage line and the base of the first transistor being connected to an output voltage line, together with the emitter of the second transistor via a second resistor, an inhibit switch comprising a third transistor being connected between the base of the second transistor and a zero voltage line, a third resistor and second capacitor being connected in parallel between the zero voltage line and the output voltage line, the arrangement being such that on application of a voltage greater than the threshold voltage of the first transistor successive positive and negative cycles alternately reverse bias and forward bias the first and second transistors to achieve a balance between the half cycle charging through the second resistor and