Abstract: An improved switching arrangement 10 for waveguide is disclosed which comprises, in combination, a coaxial switch 12 and a unified, multi-port, waveguide interface 14. The coaxial switch 12 has coaxial connectors of a first type (12a, 12b, 12c) mounted in a parallel pattern with a preestablished center-to-center spacing. The waveguide interface 14 includes flanges (14a, 14b, 14c), and is preferably formed as a waveguide housing having a transition plate portion and a cover plate portion. Each port of the unified waveguide interface includes internal waveguide-to-coax transitions for coupling to a respective external connector of a second type. The external coaxial connectors (16a, 16b, 16c) are configured in a parallel pattern with center-to-center spacings equal to the preestablished center-to-center spacings of the coaxial switch connectors (12a, 12b, 12c) such that these connectors mate directly with those of the unified waveguide interface.

Abstract: An electro-optic display having either variable-color or selectable-color capability is disclosed, with each having particularly efficient electrode patterns for achieving color control. Each implements a passive display utilizing an electro-optic material such as PLZT having one of these types of electrode patterns and aligned with an appropriate multi-colored filter. By applying D.C. control voltages to these sets of electrodes, which are sufficiently small to form unit cells, variable or selectable color is perceived. The patterns may be arranged in a sequence of any length or width, with the three-shutter pattern featuring no surface-mounted crossovers.

Abstract: A notch filter as disclosed which is adaptable to notching out a background siren from voice communications from an emergency vehicle. Two embodiments are disclosed. In the first embodiment, a frequency lock loop tracks the fundamental frequency of an electronic siren. The siren fundamental frequency is then notched out from voice transmissions using a notch filter. In the preferred transmissions using a notch filter. In the preferred embodiment, a digital ramp is generated by a first digital signal processor. This signal is input to an amplifier and a speaker thus producing an electronic siren. The digital ramp is also input to a second digital signal processor which notches out the fundamental frequency and odd harmonics thereof from the digital ramp thus acting as a comb notch filter. Analog voice is digitized by way of an analog to digital converter and input to the second digital signal processor.

Abstract: A system for rapidly detecting power disturbances with ferroresonant transformers having a decay profile comprising the steps of rectifying a power signal; comparing the rectified signal against a reference signal; comparing the rectified signal against a dynamic reference signal; and generating a power-fail signal in response to either comparison falling below its respective reference.

Abstract: An ultra high density pad array chip carrier is disclosed which includes a ceramic substrate having a plurality of electrical conductors each of which connect to a respective through-hole plugged with solder on its bottom surface. These solder plugs form a pad array for the chip carrier as well as provide a hermetic seal for the ceramic substrate. A polymer dielectric layer is affixed to the top surface of the ceramic substrate which provides an insulated metal die mount pad thereon. The electrical conductors on the ceramic substrate are formed using well-known vacuum metallization techniques to achieve much narrower widths. Approximately a 40 percent reduction in overall size and cost is achieved utilizing this improved arrangement, which improves reliability and facilitates post-assembly cleaning of the chip carrier when mounted to its final board.

Abstract: An ultra high density pad array chip carrier is disclosed which includes a ceramic substrate having a plurality of electrical conductors each of which connect to a respective through-hole plugged with solder on its bottom surface. These solder plugs form a pad array for the chip carrier as well as provide a hermetic seal for the ceramic substrate. A polymer dielectric layer is affixed to the top surface of the ceramic substrate which provides an insulated metal die mount pad thereon. The electrical conductors on the ceramic substrate are formed using well-known vacuum metallization techniques to achieve much narrower widths. Approximately a 40 percent reduction in overall size and cost is achieved utilizing this improved arrangement, which improves reliability and facilitates post-assembly cleaning of the chip carrier when mounted to its final board.

Abstract: A simulcast transmitter apparatus having automatic synchronization capability is disclosed which utilizes a signal readily available from any one of a number of available master timing sources to maintain a constant, uniform time delay to the transmitter via its interconnect link, even though the time delay corresponding to this interconnect link is susceptible to variation. Each interconnect link may consist of a phone line or other radio link which exhibits a relatively fixed, but unstable, delay. Each base station includes at least a transmitter and an adaptive-delay device which operates as a remotely-adjustable delay network upon receipt of a resync signal from a central controller to readjust and automatically maintain a uniform amount of time delay to each transmitter in the base stations.

Abstract: An improved simulcast transmission system having automatic synchronization is disclosed which utilizes a signal from any one of a number of readily available master timing sources to maintain a constant, uniform time delay to a multiplicity of transmitters even though the time delay corresponding to an included individual interconnect link is susceptible to variation. This simulcast system includes a central controller for controlling, via an interconnect link, the operation of each transmitter located at a plurality of base station sites. This central controller includes a master timing signal receiver and periodically outputs a resynchronization command via the interconnect link to the base stations. Each interconnect link may consist of a phone line or other radio link which exhibits a relatively fixed, but unstable, delay.

Abstract: A register-modelled radio system comprising a plurality of register-modelled processors having addressable registers for modelling the virtual state of the processor; a serial bus, interconnecting the register-modelled processors for communicating between the addressable registers; and a communications protocol for passing information to or from the addressable registers, whereby the virtual state of a radio portion may be determined or altered by, respectively, communicating information from or to the addressable registers. The communications protocol further comprises an information packet having an address, an operation code, optional data, and an error detection device, such as a cyclical redundancy check packet. The operation code is chosen from the group of primitive operation codes reset, read, write, bit set, bit clear, acknowledge, and negative acknowledge.

Abstract: An improved synchronization method and apparatus is disclosed which derives a common reference signal from a pilot frequency which is embedded among other signal information and which may be preselected from among a group of possible pilot frequencies utilized in multiplexing and demultiplexing groups of information signals on a RF communication system. One such arrangement as disclosed provides for rapid phase-lock acquisition with very few functional blocks by utilizing a linear multiplier as a phase detector at the generally higher pilot frequency rather than the much lower reference frequency. Another embodiment discloses a method and arrangement for providing automatic leveling of the pilot frequency input signal using a second linear multiplier as an amplitude detector.

Abstract: An improved fault detect algorithm and circuit is disclosed which quickly evaluates substantially all the elements within a successive approximation A/D convertor without resorting to off-line measurements. This method utilizes a small alternating offset signal injected into the correction loop in addition to the already converted value to determine whether the elements within this loop are operating properly for any in range analog input value.

Abstract: A maximum distance from zero-crossing demodulation method for MSK or OK-QPSK signals is disclosed which utilizes the zero-crossing information for establishing a bit edge reference and an optimum sampling point situated essentially midway between the zero-crossings of the higher of the two incoming signalling tones. This method is able to provide improved noise immunity over other known methods by at least an additional 10 degrees of phase margin while conserving processor steps during the phase detection process.

Abstract: A method within adjusting values of a passive temperature compensation network for use in an oscillator includes the steps of determining the frequency variation of the oscillator from nominal over a specified temperature range, determining the maximum frequency variation over the temperature range, and recalculating the performance of the circuit over the temperature range utilizing reduced values for the temperature compensation components therein. The oscillation frequency can be utilized as the controlled parameter to a laser based component trimming system. Power is applied to the oscillator and the compensation component is trimmed until the circuit oscillates at the specified target frequency.

Abstract: A method and means for quadrature amplitude modulation is described. The improved QAM modulator circuit utilizes a small read only memory to hold multiple versions of a signal constellation resulting in the elimination of hardware modulator circuits. In addition, the described device can be potentially any modulation scheme on an input signal which is sampled in time by modifying the contents of said ROM.

Abstract: An improved mounting system for surface mounted components is described. The mounting system of the present invention provides preparations for surface mounted components and the printed circuit substrate which render the resultant assembly highly resistant to stresses which occur due to thermal cycling. The printed circuit substrate is conditioned by removing selected areas of media surrounding the points of attachment between the surface mounted component and the printed circuit media. In addition, a spacing element is disposed between the surface mounted component and the printed circuit media to promote the formation of a virtual lead during assembly.

Abstract: In accordance with the present invention there is provided a common antenna signal path selectively coupled to a plurality of signal energy paths, including transmitter and receiver paths. The transmitter and receiver paths are selectively coupled to the common antenna signal path by semiconductive devices capable of being variably biased from conductive to nonconductive states. In the transmit mode, the magnitude of the RF signal energy is detected and developed to adaptively maintain the disabled semiconductive device in a reverse biased or nonconducting state.

Abstract: In accordance with the present invention, there is provided a register-modelled radio system comprising a plurality of register-modelled processors having addressable registers for modelling the virtual state of the processor; a serial bus, interconnecting the register-modelled processors for communicating between the addressable registers; and a communications protocol for passing information to or from the addressable registers, whereby the virtual state of a radio portion may be determined or altered by, respectively, communicating information from or to the addressable registers. The communications protocol further comprises an information packet having an address, an operation code, optional data, and an error detection device, such as a cyclical redundancy check packet. The operation code is chosed from the group of primitive operation codes reset, read, write, bit set, bit clear, acknowledge, and negative acknowledge.

Abstract: An interface circuit is coupled between the last stage of an FSK receiver and a limiter to provide a biasing voltage signal to the limiter. The receiver includes a power saver circuit which supplies power on an interrupted basis. The interface circuit contains maximum and minimum detectors which derive and hold voltages corresponding to the maximum and minimum values of the discriminated signal from the receiver. These maximum and minimum corresponding voltages are averaged in a predetermined manner to provide the biasing voltage to the limiter. Thus, a proper bias voltage level can be accurately and quickly determined, and supplied to the limiter when power is supplied.

Abstract: A frequency synthesized transceiver capable of tuning to a plurality of communication channels is disclosed. The transceiver includes a receiver and a transmitter section which are coupled to the synthesizer which generates the appropriate injection signals to achieve tuning. A battery saving circuit generates a battery saving signal having a predetermined duty cycle and period and is responsive to the phase detector in the synthesizer to disrupt power to the synthesizer while maintaining precise tuning. The battery saver circuit is also responsive to the transceiver. In a normal receive operation, a battery saving circuit synchronizes its battery saving signal with the hold condition of the phase detector to disrupt power to selected modules in the synthesizer without altering the injection frequency of the receiver. In a standby mode, power is disrupted to all modules in the receiver, the selected modules in the phase locked loop and the voltage controlled oscillator.