Abstract: A relatively compact cooking assembly includes means for selectively positioning a cooking element above several cooking zones of a lower grill. In addition to a lower heated metal surface having several cooking zones, which may be delineated by vertical barriers or splash plates, the system includes an upper assembly comprising an upper member in which a radiant heating element is positioned, said assembly being adapted to fit over the back splash plate of the grill and extending the depth (back to front) of the grill, and further adapted to be raised or lowered and selectively raised or lowered as well as positioned by a sliding motion above a designated zone in predetermined sequence.
Abstract: Method and apparatus for conditioning participants in games of billiards or the like to visualize the geometry underlying the pocketing of an object ball as the result of impact by a cue ball through respective employment of a training device. The device adapted to be positioned above the playing surface and out of the field of play, the device consists of support and platform members, said plataform member rotatable in a horizontal plane housing three laser light-emitting means, the first being projected downwardly to illuminate a selected object ball, the second downwardly projecting a line path from the illuminated object ball to the designated target, and the third is directed downwardly to emit a beam projected on the “aim spot,” whereby the cue ball is propelled over the “aim spot” impacting the object ball causing the objet ball to travel along the illuminated line path to the designated target.
Abstract: A device for simultaneously and evenly toasting articles of differing contours and dimensions arranged upon a heated griddle. A clamshell plate, positioned in stand-off relationship above said griddle-arranged articles, has a plurality of slideably moveable fingers or pins mounted therein which float, that is, are brought into contacting and resting relation with the upper surfaces of said articles to provide a gentle pressure thereon to urge the lower surfaces into more intimate contact with the griddle until the toasting process is completed, thereby accelerating the toasting process without undesirable side effects such as distortion of, and condensation on, the upper surfaces and caramelization of the lower surfaces of said articles.
Abstract: An ergonomically-designed, operator manipulated scraper means for contacting a cooking surface for the purpose of dislodging and/or removing unwanted material therefrom. A griddle scraper has a platform member, the downwardly distending forward portion of which comprises a cleaning means terminating in a blade edge, and the rear portion of which extends in an upwardly direction. A support member connects at its lower end to said platform and extends upwardly, having a rearwardly inclined end portion. A “handshake grip” handle positioned above said platform interconnects the support member to said upwardly extending rear portion of said platform. A knob handle is mounted on the support member upper end.
Type:
Grant
Filed:
September 27, 1999
Date of Patent:
July 24, 2001
Assignee:
In-N-Out Burgers
Inventors:
Howard Jay Frantz, Christopher Paul Lojacono
Abstract: An optically intraconnected computer and a reconfigurable holographic optical element employed therein. The basic computer comprises a memory for holding a sequence of instructions to be executed; logic for accessing the instructions in sequence; logic for determining for each the instruction the function to be performed and the effective address thereof; a plurality of individual elements on a common support substrate optimized to perform certain logical sequences employed in executing the instructions; and, element selection logic connected to the logic determining the function to be performed for each the instruction for determining the class of each function and for causing the instruction to be executed by those the elements which perform those associated the logical sequences affecting the instruction execution in an optimum manner. In the optically intraconnected version, the element selection logic is adapted for transmitting and switching signals to the elements optically.
Abstract: In a multicomputer, concurrent computing system having a plurality of computing nodes, this is a method and apparatus for routing message packets between the nodes.
Abstract: This invention is primarily a "resistive fuse" circuit, being a hardware circuit that explicitly implements either analog or binary line processes in a controlled fashion.
Abstract: A CMOS analog integrated circuit comprising a plurality of nodes for simultaneously computing the largest of the signals at inputs of the nodes. There is a common line supplying current and producing a maximum voltage potential and a plurality of nodes connected to the common line. Each node comprises a follower transistor having a source operably connected to the common line for sourcing current and a gate being the input of the node and being connected to a current signal input source providing a current signal to the node to be compared to the current signals at respective ones of the other nodes. There is an inhibitor transistor having a gate connected to the common line and a drain operably connected to the gate of the follower transistor. The inhibitor transistor provides the voltage output of the node and inhibits the voltage output at all nodes connected to the common line which have a current signal which is smaller than the largest current signal connected to one of the nodes.
Type:
Grant
Filed:
November 30, 1988
Date of Patent:
October 22, 1991
Assignee:
The California Institute of Technology
Inventors:
Carver A. Mead, John Lazzaro, M. A. Mahowald, Sylvie Ryckebusch
Abstract: An improved communication system for the prevention of lockup in a computer system of the binary n-cube type. Input circuitry at each of the nodes is connected for receiving messages and includes an input buffer for initially receiving the messages. Output circuitry at each of the nodes is connected for transmitting holding the messages prior to and during transmission thereof. A kernel program at each of the nodes acts as an interface between the user process programs and exclusively controls the receiving and transmitting of messages into and out of the node. There is provision for the user process programs to pass control to the kernel program to request the sending and receiving of messages by the kernel program. A lock bit is associated with each message, sensible by the user process programs, and reset by the kernel program when the kernel program has transferred the associated message.
Type:
Grant
Filed:
January 31, 1989
Date of Patent:
September 10, 1991
Assignee:
The California Institute of Technology
Inventors:
William C. Athas, Reese Faucette, Charles L. Seitz
Abstract: A method and associated apparatus for accessing a plurality of DRAMs in the static column mode by a high performance instruction processor to provide minimum wait state accessing thereby.
Type:
Grant
Filed:
June 2, 1988
Date of Patent:
June 26, 1990
Assignee:
The California Institute of Technology
Inventors:
Craig S. Steele, William C. Athas, Jr., Charles L. Seitz
Abstract: A deadlock-free routing system for a plurality of computers ("nodes") is disclosed wherein each physical communication channel in a unidirectional multi-cycle network is split into a group of virtual channels, each channel of which has its own queue, one at each end. Packets of information traversing the same physical channel are assigned a priority as a function of the channel on which a packet arrives and the node to which the packet is destined. The packet's priority is always increasing as it moves closer and closer to its destination. Instead of reading an entire packet into an intermediate processing node before starting transmission to the next node, the routing of this invention forwards every flow control unit (flit) of the packet to the next node as soon as it arrives. The system's network is represented as a dependency graph, which graph is re-ordered to be cycle free.
Abstract: A random access memory addressing system utilizing optical links between memory and the read/write logic circuits comprises addressing circuits including a plurality of light signal sources, a plurality of optical gates including optical detectors associated with the memory cells, and a holographic optical element adapted to reflect and direct the light signals to the desired memory cell locations. More particularly, it is a multi-port, binary computer memory for interfacing with a plurality of computers. There are a plurality of storage cells for containing bits of binary information, the storage cells being disposed at the intersections of a plurality of row conductors and a plurality of column conductors. There is interfacing logic for receiving information from the computers directing access to ones of the storage cells. There are first light sources associated with the interfacing logic for transmitting a first light beam with the access information modulated thereon.
Type:
Grant
Filed:
February 19, 1988
Date of Patent:
November 28, 1989
Assignee:
California Institute of Technology
Inventors:
Alan R. Johnston, Robert H. Nixon, Larry A. Bergman, Sadik Esener