Abstract: A precision trim circuit for a tuneable delay line is provided. The precision trim circuit provides delays greater than the base delay of the tuneable delay line. By using larger delays than conventional trim circuits, the precision trim circuit of the present invention can use components that react to process and environmental variations in the same manner as the components of the tuneable delay line. Specifically, one embodiment of the precision trim circuit comprises a first delay element providing a delay greater than or equal to the base delay of the tuneable delay line. The precision trim circuit also comprises a second delay element providing a greater delay than the first delay element. A multiplexer coupled to the first delay element and the second delay element is used to select the amount of delay provided by the precision trim circuit. Other embodiments include additional delay elements providing varying delay values.

Abstract: A power-on reset circuit is provided which uses a dual voltage detection circuit to output a voltage detection signal. The dual voltage detection circuit is coupled to a first supply voltage terminal, a second supply voltage terminal, and a ground terminal. The voltage detection signal indicates whether the first supply voltage provided on the first supply voltage terminal is greater than an adequate voltage level. Furthermore, the voltage detection signal is driven by circuits powered by a second supply voltage provided on the second supply voltage terminal. One embodiment of the dual-voltage detection circuit comprises a first transistor coupled in series with a second transistor between the first supply voltage terminal and the ground terminal, as well as a third transistor coupled in series with a fourth transistor between the second supply voltage terminal and the ground terminal.

Abstract: A method is provided for configuring an FPGA using a decoder implemented in the FPGA. Specifically, an external configuration device or an embedded non-volatile memory configures a first portion of the FPGA as a decoder. Encoded configuration data is transferred to the decoder, which then configures other portions of the FPGA. In one embodiment, the decoder is a decompression unit, which decompresses compressed configuration data. In another embodiment, the decoder is an interpreter, which interprets configuration commands. In some embodiments, the portion of the FPGA used for the decoder can be reconfigured after the configuration of the other portions of the FPGA.