Abstract: A method for fabricating a FET transistor for an integrated circuit by the steps of forming recesses in a substrate on both sides of a gate on the substrate, halo/extension ion implanting into the recesses, and filling the recesses with embedded strained layers comprising dopants for in-situ doping of the source and drain of the transistor. The stress/strain relaxation of the resulting transistor is reduced.

Abstract: A method and resulting structure for fabricating a FET transistor for an integrated circuit on a silicon oxide (SOI) substrate comprising the steps of forming recesses in a substrate on both sides of a gate on the substrate, implanting oxygen ions into the recesses, and annealing the substrate to convert the oxygen ions into a SOI layer below each recess.

Abstract: A method for forming preferably Pb-lead C4 connections or capture pads with ball limiting metallization on an integrated circuit chip by using a damascene process and preferably Cu metallization in the chip and in the ball limiting metallization for compatibility. In two one embodiment, the capture pad is formed in the top insulating layer and it also serves as the final level of metallization in the chip.

Abstract: Multilevel metallization layouts for an integrated circuit chip including transistors having first, second and third elements to which metallization layouts connect. The layouts minimize current limiting mechanism including electromigration by positioning the connection for the second contact vertically from the chip, overlapping the planes and fingers of the metallization layouts to the first and second elements and forming a pyramid or staircase of multilevel metallization layers to smooth diagonal current flow.

Abstract: A method and apparatus for determining the complete coverage of a passivating material on the final conductive interconnection of a wafer containing integrated circuits. A test structure with the dimensions of the final interconnections of the integrated circuits is formed during manufacture of the integrated circuits and used to determine complete coverage of the wafer by creating an opening in the passivating material at the test structure, the size of the opening being indicative of the complete coverage of the wafer.

Abstract: A process and apparatus for removing flip chips with C4 joints mounted on a multi-chip module by applying a tensile force to one or more removal member bonded to the back of one or more flip chips during heating of the module to a temperature sufficient to cause the C4 joints to become molten. The tensile force can either be a compressed spring, or a bi-metallic member which is flat at room temperature and becomes curved when heated to such temperature, or a memory alloy whose original shape is curved and which is bent flat at room temperature but returns to its original curved shape when heated to such temperature. An adhesive is used to bond the removal member to the chip to be removed and is a low temperature, fast curing adhesive with high temperature tolerance after curing.

Abstract: A process and apparatus for removing flip chips with C4 joints mounted on a multi-chip module by applying a tensile force to one or more removal member bonded to the back of one or more flip chips during heating of the module to a temperature sufficient to cause the C4 joints to become molten. The tensile force can either be a compressed spring, or a bimetallic member which is flat at room temperature and becomes curved when heated to such temperature, or a memory alloy whose original shape is curved and which is bent flat at room temperature but returns to its original curved shape when heated to such temperature. An adhesive is used to bond the removal member to the chip to be removed and is a low temperature, fast curing adhesive with high temperature tolerance after curing.

Abstract: This invention relates to a circuit for holding a pulse at an up level during a time interval .tau. after the input signal has been removed, and to the use of the circuit to realize a monostable multivibrator. The holding circuit features a bipolar transistor that is driven into saturation by the application of an input signal in the form of a clock pulse. The hold circuit also features a control network including a diode and a drain resistor. Upon removal of the input signal the charge stored in the base of the saturated transistor is caused by the diode to flow in a controlled manner to the drain resistor so that the transistor is cut off after a time interval .tau. closely approximating the storage time t.sub.s. Thus, the holding circuit provides a pulse of width T+.tau.. A monostable multivibrator is obtained by connecting the holding circuit to one of the two inputs of a conventional NOR circuit. The other NOR circuit input receives the input clock pulse.

Abstract: A variable axis immersion lens electron beam projection system shifts the electron beam while eliminating rapidly changing fields, eddy currents and stray magnetic fields in the target area. The electron beam projection system includes an electron beam source and a deflection means. A variable axes immersion lens for focusing the electron beam includes an upper pole piece, and a lower pole piece having a non-zero bore section, a zero bore section and an opening therebetween for inserting the target into the lens. The variable axis immersion lens provides an axial magnetic projection field which has zero first derivative in the vicinity of the target area. A magnetic compensation yoke, positioned within the bore of the upper pole piece produces a magnetic compensation field which is proportional to the first derivative of the axial magnetic projection field.

Abstract: An improved lift-off process for multilevel metal structure in the fabrication of integrated circuits by employing lift-off layer formed from polymers which undergo clean depolymerization under the influence of heat or radiation and allow rapid and residue-free release of an "expendable mask". An embedded interconnection metallurgy system is formed by application of the lift-off layer of this invention over a cured polymer film or on an oxygen RIE barrier layer previously deposited on organic or inorganic substrate, followed by another barrier over which is then coated a radiation sensitive resist layer.

Abstract: A test system for testing circuits in integrated circuit chips includes a host computer for controlling the test system, and a plurality of blocks operable in parallel and each including a controller, storage for test programs and test data, and plurality of electronic units or pin electronics cards, one unit being associated with one of the pins of a device under test. Each of the electronic units include timing circuitry for timing its associated pin independent of the timing of any other electronics unit.

Abstract: An electron beam method and apparatus, for writing patterns, such as on semiconductor wafers, in which the writing field is divided into a large number of overlapping subfields with a predetermined periodicity. Subfield to subfield moves are made in a stepped sequential scan, such as raster, while patterns, within a subfield, are addressed using vector scan and written using a sequential scan. Significant improvement in throughput results by the use of this electron beam method and apparatus which preferably employs magnetic deflection for the sequential scanning the subfields and electric deflection for vector scanning within the subfield.

Abstract: A device for storing and displaying graphic information having a storage unit for storing both blocks and rows of data and retrieving rows of data. The storage unit consists of two storage segments, with eight storage modules each, which can operate in an interleaved mode. This permits two-dimensional addressing which consists of distributing the individual elements of a data block over the various separately addressable modules of the storage unit so that no one module contains more than one element of the data block, and that all elements of the data block can be read out in one cycle through simultaneous access of all of the storage modules.

Abstract: A manufacturing processing system comprises a plurality of processing stations, preferably vacuum stations, interconnected by air track, preferably an axi-radial air track with novel sections rotatable about a transverse axis in the plane of the track and normal to the travel of the objects, hereafter referred to as swivelators. Certain of the swivelators are formed with axial movable portions capable of moving beyond the plane of the air track surface and returning to the plane, so that these swivelators can pick up and set down objects in predetermined positions in the manufacturing processing station with an air force so as to not make physical contact with the objects. A novel gas lock device is positioned in the air track between those processing stations, in which the gas pressure must be separated so as to essentially eliminate the possibility of gas contaminant passing from one station to the next.

Abstract: A 3-way Exclusive OR function is performed in an essentially single stage logic delay. A 3-way OR circuit produces a logical "1" output whenever at least one of three input operands is "1". A Two And Only Two logic circuit produces a logical "0" output when two and only two of the three input operands are "1". The outputs of the OR circuit and the Two And Only Two logic circuits are DOT-ANDed to provide a desired Exclusive OR function. In one form of the invention, the Two And Only Two logic circuit comprises three Schottky diode transistor NAND circuits each having two normal inputs and one inhibit input with the inhibit input of each of the three NAND circuits being connected to receive a different one of the three input operands while the two normal inputs being connected to receive the remaining ones of the three input operands. The OR circuit comprises four transistors having their emitters coupled to a common current source.

Abstract: A rapid, non-destructive system and method for insitu detection and identification of luminescent organic particulates or films on non-luminescent devices, such as semiconductor wafers and chips. The major optical components of the system comprises a luminescent vertical illuminator, an image device and a detector. The method is based on the principle that a very large number of organic materials luminesce when excited by ultraviolet radiation. By scanning the luminescent emission spectra of the known organic materials used in manufacture, a characteristic curve of intensity versus wavelength is obtained and matched to curves of known organic materials, thereby permitting detection and identification of the particulates.

Abstract: Apparatus for monitoring the product temperature in an open ended furnace of the secondary emission type, the furnace having a plurality of serially arranged heating zones therein and including a conveyor which passes through the muffle of the furnace for carrying product thereon through the furnace. The furnace includes apparatus for adjusting the temperature in each of the zones. At least one cable passes through the furnace superimposed of the conveyor and carries thereon a plurality of temperature sensors which are serially arranged along the cable. The sensors are connected externally of the furnace to provide external monitoring of the temperatures in at least preselected zones (critical zones) of the furnace while the cable is provided with sag inhibiting apparatus to keep tension on the cable when the furnace is in operation.

Abstract: A method for fabricating bipolar semiconductor devices of large scale integration in which the formation of pipes, which result in shorts or leakages between two conductivity types of the semiconductor devices, is minimized. Prior to forming the emitters in the bipolar transistors, nucleation sites for crystallographic defects such as dislocation loops are formed in the base region near its surface. The emitters are then formed in base regions containing the nucleation sites and the sites are converted into electrically harmless dislocation loops during diffusion of the emitter impurity. Preferably, the nucleation sites are formed by implanting non-doping impurities, such as helium, neon, argon, krypton, xenon, silicon, and oxygen.

Abstract: Apparatus for monitoring product temperature in a furnace, the furnace being of the open ended and secondary emission type, and having a plurality of serially arranged heating zones therein, each of the zones being adjustably heated. The furnace includes a conveyor which passes therethrough for carrying product thereon through the furnace. As is conventional, the furnace includes an outer casing or wall and an inner muffle with a cavity therebetween. Heaters are provided for applying heat to the cavity to heat the wall of the muffle. Tubes are provided for passing through the casing and into the muffle so that temperature sensing means may pass through the tubes into the muffle superimposed of the conveyor. The temperature sensors are connected to a monitoring system for amplification and for monitoring the temperatures directly of at least the critical zones of the furnace so that adjustment of the temperature may be made within preselected zones without causing loss of product.