Patents Represented by Attorney, Agent or Law Firm Edwin H. Paul
  • Patent number: 7834378
    Abstract: A composite dual SCR circuit that acts to protect the Vcc node as well as an I/O node or pin. The dual SCR uses the Vcc to control or program the triggering point of the SCR connected to an I/O node. When Vcc is low, the SCR protecting an I/O node triggers a few volts above ground, but when Vcc is high the trigger point of the SCR protecting the I/O node is much higher. The dual SCR incorporates added diffusions to an existing first SCR structure between the power node and the ground node thereby forming a second SCR. The first and second SCRs share a common cathode transistor. In one illustrative embodiment, only one SCR is constructed incorporating the Vcc to control the triggering of the SCR.
    Type: Grant
    Filed: August 28, 2007
    Date of Patent: November 16, 2010
    Assignee: Fairchild Korea Semiconductor Ltd
    Inventors: Junhyeong Ryu, Taeghyun Kang, Moonho Kim
  • Patent number: 7378886
    Abstract: A supply voltage level detection circuit makes use of an additional supply already provided for power. A voltage detection circuit defines a first threshold, and a differencing circuit defines a second threshold. The output state of the differencing circuit is saved in a latch. The latch may be cross coupled gates of cross coupled inverters. When inverters are used, the differencing circuit output contends with the internal latch drive when setting or resetting the latch. The design allows the differencing circuit to overcome the inverter's internal drives to change the logic state of the latch.
    Type: Grant
    Filed: October 14, 2004
    Date of Patent: May 27, 2008
    Inventor: Gregory A. Maher
  • Patent number: 6836810
    Abstract: A backplane bus system and related method for increasing the throughput of cPCI-specified backplane architectures. The system includes an interposer card for transforming reflective-wave switching into incident-wave switching. Establishing incident-wave switching on the bus along with careful slot pitch and impedance layout increases the rate at which the voltage amplitude observed by all receivers connected to the bus is sufficient to produce a change of state on the first signal propagation down the bus. Most existing peripherals are configured with transceivers that produce reflective-wave switching. The present system includes an interposer card to transform that switching into incident-wave switching. A preferred transceiver for doing so and that is implemented on the interposer card is a GTLP transceiver. A state machine is employed to regulate operation of the incident-wave switching transceiver. The system may be used to permit implementation of as many as 21 slots on a conventional cPCI backplane.
    Type: Grant
    Filed: March 29, 2001
    Date of Patent: December 28, 2004
    Assignee: Fairchild Semiconductor Corporation
    Inventors: R. Craig Klem, Carl R. Poirier
  • Patent number: 6813209
    Abstract: A low read current, low power consumption sense amplifier well suited for low frequency RFID systems is disclosed. An MOS transistor receives the read current from a memory cell, typically an EEPROM, and a current mirror is formed by a parallel MOS transistor. The mirror current is integrated on a capacitor after the charge on the capacitor is cleared via a reset pulse. A time period is defined during which the voltage on the capacitor is compared to a second voltage. The second voltage is formed from a reference voltage or from dummy cells, in either case the reference voltage is at about the logic boundary between a one and zero stored in a memory cell. A comparator, with or without input hysteresis, receives the voltage on the capacitor and a second voltage and within the time period, the output state of the comparator indicates the binary contents of the memory cell.
    Type: Grant
    Filed: October 14, 2003
    Date of Patent: November 2, 2004
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Ethan A. Crain, Karl Rapp, Etan Shacham
  • Patent number: 6794945
    Abstract: A phase locked loop circuit is used to provide timing clocks for data bit recovery from a serial data flow. The system locks to a SYNC signal, preferably a lower frequency fifty percent duty cycle square wave with a period equal to the time of a fully framed serial data word. When a start signal transition is detected the system is prevented from trying to lock onto the data signal edge transitions. But, the system provides a signal suitable for clocking in the individual data bits.
    Type: Grant
    Filed: April 11, 2003
    Date of Patent: September 21, 2004
    Assignee: Fairchild Semiconductor Corporation
    Inventors: James J. McDonald, II, Ronald B. Hulfachor, Jim Wunderlich
  • Patent number: 6781415
    Abstract: A bi-direction voltage level translating switch that connects a higher voltage circuit to a lower voltage circuit without using a direction signal disclosed. The drive circuit for the gate of an MOS switch acts to clamp the lower voltage side of the translating switch limiting the lower voltage to a level compatible with the lower voltage circuitry connected to the lower voltage side. A pull up circuit is connected to the higher voltage side of the switch and further defines a threshold lower than the lower voltage. When the signal reaches the threshold the pull up circuit pull the higher voltage side up to the higher voltage. Again the drive on the gate of the switch prevents that higher voltage from reaching the lower voltage side. When the lower voltage side drives, through an on switch, the higher voltage side low, the pull up circuit is designed to be overcome by the lower voltage drive circuitry so that the higher voltage side goes low.
    Type: Grant
    Filed: November 21, 2002
    Date of Patent: August 24, 2004
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Sean X. Clark, James B. Boomer
  • Patent number: 6781456
    Abstract: Differential input fail safe circuitry is disclosed that detects missing or too low differential signals combined with a frequency lower than a frequency limit where a final safe condition is detected and signaled. The output signal form the fail safe circuitry is held in a given state that is an invalid representation of the differential input signal. A frequency detector, complementary offsetting auxiliary amplifiers with limit frequency roll offs are used to detect the fail safe condition. In addition a delay circuit is used that requires the fail safe condition to exist for some time before the fail safe circuit is active. Initialization circuitry ensures a proper power up conditions where the circuitry is enabled to detect the fail safe conditions and guarantees a reliable fail safe irrespective of the previous state of the signal.
    Type: Grant
    Filed: November 12, 2002
    Date of Patent: August 24, 2004
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Pravas Pradhan
  • Patent number: 6781460
    Abstract: A folder common cascode circuit with symmetric parallel signal paths from the differential inputs to the differential outputs provides a low skew, low jitter, low power differential amplifier. The signal paths on either side of the differential amplifier are made equal with equal loads along each path. Pairs of complementary NMOS and PMOS transistor pairs with parallel complementary biasing stacks on the output cascode circuitry maintain symmetrical parallel signal paths, amplification and impedance loading from differential input to differential output. Output voltage translating inverters provide a higher voltage level output signal while maintaining low skew and jitter.
    Type: Grant
    Filed: October 29, 2002
    Date of Patent: August 24, 2004
    Assignee: Fairchild Semiconductor Corp.
    Inventors: Ethan A. Crain, Pravas Pradhan
  • Patent number: 6774675
    Abstract: A bus hold circuit of CMOS components that draws no DC current and is over voltage tolerant is described. No leakage current is drawn from the input when the input voltage is greater than the bus hold circuit supply voltage. A feedback inverter is used to s latch the Vin logic in the bus hold circuit. When Vin is low, it turns on a first switch that drives the gate of a PMOS switch low turning it on. The PMOS switch connects the power connection of the feedback inverter to Vcc. The gate remains low, keeping the PMOS switch turned on as Vin increases. The first switch is turned off, but the gate of the PMOS switch remains low, until Vin exceeds Vcc. At that point, a comparator drives the gate of the PMOS to Vin shutting the PMOS switch off. An arbiter circuit selects the higher of Vcc and Vin to bias the N-well of the PMOS switch and other PMOS components in the comparator and arbiter circuit. This biasing ensures that the N-wells are never forward biased, thereby preventing leakage from the Vin.
    Type: Grant
    Filed: June 24, 2003
    Date of Patent: August 10, 2004
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Myron J. Miske, Stephen B. Lombard
  • Patent number: 6770494
    Abstract: Chemical mechanical polishing (CMP) produces thickness variations over the surface of a chip or die that depends on many factors. The present invention provides for characterization of the thickness variations over the surface area, and accepting these variations in the detailed design of the components that are to be distributed over the entire surface of the die. Any device with parameters that depend on the layer thickness that is subject to CMP will have variations in those parameters depending upon where the device is located on the die. The present invention characterizes the thickness variations and modifies the physical design of other mechanical aspects of the device so as to compensate for the thickness variations. The result is devices that have acceptable parameters regardless of their location on the chip.
    Type: Grant
    Filed: January 15, 2003
    Date of Patent: August 3, 2004
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Jason Woloszyn, Michael Harley-Stead
  • Patent number: 6756826
    Abstract: A buffer circuit with slow output edges is described. Pulsed higher value currents are driven from one shot timing circuits to inject a pulse of current into the control gate of the buffer's output MOSFET to speed up the beginning of the turning on or the turning off of the output MOSFT. When the beginning and turning on and off is reached lower value current sources continue to drive the gate of the output MOSFET. In one embodiment, one shots are triggered from the rising and falling edges of the input signal. The effect of the higher value current pulses is to reduce the circuit delay through the buffer. Also, the pulse width can be designed as temperature sensitive, and supply voltage sensitive so as to maintain the buffer circuit delay as substantially constant as temperature, supply voltage and process variation occur.
    Type: Grant
    Filed: June 12, 2003
    Date of Patent: June 29, 2004
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Christian Klein, James J. McDonald, II
  • Patent number: 6724134
    Abstract: A high intensity discharge lamp includes a dielectric substrate, a first electrode near the dielectric substrate, a second electrode spaced from the first electrode and near the dielectric substrate, with a discharge gas contained and enclosed by a shaped reflector and window. The reflector shapes are adapted to the particular process. The lamp to be used in volumetric chambers with high reflectivity walls and in arrangements of multiple lamps for high processing rates and long penetration lengths. Erosion of the dielectric is controlled by the use of high-pressure gases, and filtration and the use of electric fields reduce lamp contamination. The dielectric and electrodes are gas cooled on the outside and through the use of perforated electrodes. A small diameter tubular dielectric is used to increase light emission, improve re-imaging capability and increase the electrical impedance.
    Type: Grant
    Filed: March 26, 2002
    Date of Patent: April 20, 2004
    Assignee: Phoenix Science and Technology, Inc.
    Inventor: Raymond B. Schaefer
  • Patent number: 6700433
    Abstract: The present application and invention provides a selectively enabled bias for the pass NMOS transistor (10) of an RF switch. Two bias supplies are selectively switched to connect to the source of the NMOS transistor (10). The first higher bias supply turns the NMOS transistor (10) off and the second lower bias supply turns the NMOS transistor (10) on. The selective switch performs a single pole double throw function and may include PMOS transistors (14, 16) with inverse logic signals connected respective gates. Diodes may be used between the PMOS and the NMOS gate to reduce the capacitance load at the NMOS gate. The bias circuitry provides for lower capacitance values in the NMOS transistor (10) for reducing insertion loss, and lower parasitic input to output capacitance thereby providing better isolation when the switch is off. Moreover, when the switch is on the source to substrate and the drain to substrate capacitances are decreased thereby providing better high frequency isolation.
    Type: Grant
    Filed: March 11, 2003
    Date of Patent: March 2, 2004
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Philip C. Zuk
  • Patent number: 6700474
    Abstract: A resistor structure is disclosed that is constructed out of two layers of polysilicon. The intrinsic device is made using the top layer which is either a dedicated deposition, or formed as part of an existing process step such as a base epi growth in a BiCMOS flow. This poly layer can be made with a relatively high (greater than 2000 ohms per square) sheet resistance by appropriate scaling of the implant dose or by insitu doping methods. The resistor ends are formed by the addition of a bottom poly layer in a self aligned manner with a deposition which may already be part of the process sequence. The end result is that the intrinsic resistor body is formed of a single poly layer, while the ends are created out of two layers. These ends are thick enough so that standard silicide and contact etch processing may be added to the structure without special care.
    Type: Grant
    Filed: August 22, 2002
    Date of Patent: March 2, 2004
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Steven M. Leibiger
  • Patent number: 6687189
    Abstract: An impulsive acoustic and radiation source is provided that maintains a constant electrode gap to provide efficient and long life operation. In one implementation the electrodes have a “toaster” arrangement. In another implementation the electrodes have a double annulus arrangement. The electrode gap may be maintained by interposing a non-electrically conducting material between the electrodes. In another implementation the electrode gap is maintain by the insertion of electrodes into a base. Also, the electrodes may be coated with a non-electrically conduction material. In alternative implementation, efficient and long life operation is achieved by feeding a material between widely spaced electrodes. In certain implementations an exothermic material is fed to increase the strength of the impulse from the sparker. Also, reflectors and enclosures are employed that increase the output utilization of the source.
    Type: Grant
    Filed: April 2, 2002
    Date of Patent: February 3, 2004
    Assignee: Phoenix Science and Technology, Inc.
    Inventors: Raymond B. Schaefer, John Gallagher
  • Patent number: 6682601
    Abstract: A programmable electronic fluid dispenser with computer controlled direct drives of a motor, connecting rod, and attached piston in a yringe is used to dispense accurate quantities of liquids with varying viscosities. The pistons are driven to dispense an amount and then the piston is reversed, overcoming any mechanical backlash, to prevent any leakage or oozing from the dispenser tip. A computer controls several dispensers cwith their outputs co-mingled. The desired proportions controlled by the computer driving the pistons.
    Type: Grant
    Filed: April 25, 2001
    Date of Patent: January 27, 2004
    Assignee: Fishman Corporation
    Inventor: W. Scott Beebe
  • Patent number: 6676642
    Abstract: A stabilizer for a piston that strengthens the piston when higher dispensing volumes and/or pressures are involved. The stabilizer intimately contacts the piston along the radius of the piston to prevent distortion of the piston thereby preventing the fluid being dispensed from flowing around the piston destroying repeatability, accuracy and contaminating the driving mechanisms. The stabilizer also prevents the piston from cocking that may make the dispensing inaccurate and non-repeatable. The stabilizer may be of substantially any material from metals to any of the plastics suitable for maintaining its structural integrity under the pressures and forces involved.
    Type: Grant
    Filed: July 10, 2001
    Date of Patent: January 13, 2004
    Assignee: Fishman Corporation
    Inventor: W. Scott Beebe
  • Patent number: 6672729
    Abstract: A reflector employs shapes that transfer light and sound emission from sources to planes or volumes in an efficient and controlled manner. Reflector troughs employ shaped ends that increase the efficiency of utilizing output from sources, improve uniformity and project light outside the footprint of the reflector. A slanted trough reflector projects light out one or both ends of the trough outside the footprint of the reflector. Axi-symmetric and linear-symmetric reflectors provide directionality for specific applications. Sources that erode are enclosed by shaped reflectors to maintain directionality as the source erodes.
    Type: Grant
    Filed: April 18, 2002
    Date of Patent: January 6, 2004
    Assignee: Phoenix Science and Technology, Inc.
    Inventor: Raymond B. Schaefer
  • Patent number: 6670822
    Abstract: A transceiver driver for shaping an output signal includes one or more capacitive elements designed to manipulate the current applied to the control node of the driver's output transistor. The capacitive elements may be one or more capacitors coupled to an inverter branch that provides turn-on and turn-off potential to the gate of the output transistor. The capacitive elements act to charge or discharge the transistor's gate gradual in a highly programmable way so as to make the driver substantially independent of fabrication, supply voltage, and operating temperature vagaries.
    Type: Grant
    Filed: August 11, 1998
    Date of Patent: December 30, 2003
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Oscar W. Freitas
  • Patent number: 6646840
    Abstract: An ESD protection device including a compound transistor structure having a trigger transistor and an ESD protection transistor. The trigger transistor includes a breakdown potential between the standoff voltage of a circuit to be protected and the breakdown potential of the ESD protection transistor. When activated, the trigger transistor operates to turn on the ESD protection transistor that is designed to carry the bulk of the conduction current associated with an ESD event. The trigger transistor is designed with an internal gain mechanism to ensure that it will not be turned off when a modified snapback voltage is reached during the ESD protection transistor operation. The trigger transistor is a minor contributor to the conducting current with the ESD protection transistor after such time as protection circuit operation acts. A process for fabricating a suitable compound transistor structure is disclosed.
    Type: Grant
    Filed: August 3, 2000
    Date of Patent: November 11, 2003
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Alvin Sugerman, Raymond Roberts, Michael Harley-Stead