Patents Represented by Attorney, Agent or Law Firm Eisa K. Jorgenson
  • Patent number: 6784042
    Abstract: An integration process in a SOI substrate of a semiconductor device having at least a dielectrically insulated well, the process including: an oxidizing step directed to form an oxide layer; a depositing step of a nitride layer onto the oxide layer; a masking step, carried out onto the nitride layer using a resist layer and directed to define suitable photolithographic openings for forming at least one dielectric trench effective to provide side insulation for the well; an etching step of the nitride layer and oxide layer, as suitably masked by the resist layer, the nitride layer being used as a hardmask; a step of forming the at least one dielectric trench, which step comprises at least one step of etching the substrate, an oxidizing step of at least sidewalls of the at least one dielectric trench, and a step of filling the at least one trench with a filling material; and a step of defining active areas of components to be integrated in the well, being carried out after the step of forming the at least one d
    Type: Grant
    Filed: December 28, 2001
    Date of Patent: August 31, 2004
    Assignee: STMicroelectronics S.r.l.
    Inventor: Leonardi Salvatore
  • Patent number: 6596555
    Abstract: A method of forming, on a single-crystal semiconductor substrate of a first material, quantum dots of a second material, including growing by vapor phase epitaxy the second material on the first material in optimal conditions adapted to ensuring a growth at a maximum controllable rate. In an initial step, a puff of a gas containing the second material is sent on the substrate, in conditions corresponding to a deposition rate much faster than the maximum controllable rate.
    Type: Grant
    Filed: August 3, 2001
    Date of Patent: July 22, 2003
    Assignee: STMicroelectronics S.A.
    Inventors: Daniel Bensahel, Olivier Kermarrec, Yves Campidelli