Abstract: This invention is primarily a "resistive fuse" circuit, being a hardware circuit that explicitly implements either analog or binary line processes in a controlled fashion.

Abstract: A CMOS analog integrated circuit comprising a plurality of nodes for simultaneously computing the largest of the signals at inputs of the nodes. There is a common line supplying current and producing a maximum voltage potential and a plurality of nodes connected to the common line. Each node comprises a follower transistor having a source operably connected to the common line for sourcing current and a gate being the input of the node and being connected to a current signal input source providing a current signal to the node to be compared to the current signals at respective ones of the other nodes. There is an inhibitor transistor having a gate connected to the common line and a drain operably connected to the gate of the follower transistor. The inhibitor transistor provides the voltage output of the node and inhibits the voltage output at all nodes connected to the common line which have a current signal which is smaller than the largest current signal connected to one of the nodes.

Abstract: An improved communication system for the prevention of lockup in a computer system of the binary n-cube type. Input circuitry at each of the nodes is connected for receiving messages and includes an input buffer for initially receiving the messages. Output circuitry at each of the nodes is connected for transmitting holding the messages prior to and during transmission thereof. A kernel program at each of the nodes acts as an interface between the user process programs and exclusively controls the receiving and transmitting of messages into and out of the node. There is provision for the user process programs to pass control to the kernel program to request the sending and receiving of messages by the kernel program. A lock bit is associated with each message, sensible by the user process programs, and reset by the kernel program when the kernel program has transferred the associated message.

Abstract: A method and associated apparatus for accessing a plurality of DRAMs in the static column mode by a high performance instruction processor to provide minimum wait state accessing thereby.

Abstract: A deadlock-free routing system for a plurality of computers ("nodes") is disclosed wherein each physical communication channel in a unidirectional multi-cycle network is split into a group of virtual channels, each channel of which has its own queue, one at each end. Packets of information traversing the same physical channel are assigned a priority as a function of the channel on which a packet arrives and the node to which the packet is destined. The packet's priority is always increasing as it moves closer and closer to its destination. Instead of reading an entire packet into an intermediate processing node before starting transmission to the next node, the routing of this invention forwards every flow control unit (flit) of the packet to the next node as soon as it arrives. The system's network is represented as a dependency graph, which graph is re-ordered to be cycle free.