Abstract: A system converts PAL and NTSC pixel clock signals to signals (in a studio, digital or square pixel format) at a sub-carrier frequency individual to the PAL and NTSC formats. The system includes a first register for providing a particular increase in the register count upon each occurrence of a pixel clock signal. Any remainder in the first register upon the production of the output signal is introduced to the register upon the occurrence of the next pixel clock signal. The particular increase in the first register count is controlled by a value in a second register, this value being adjustable dependent upon the system format and mode. A sequence of registers may be substituted for the first register with each register receiving an output from the previous register in the sequence. The system also converts signals representing the primary colors to luminance and chrominance signals.