Abstract: A memory circuit that reduces memory operation access time and stress on the memory cells due to memory operations. The memory circuit comprises a semiconductor memory array having a continuously addressable memory space being divided into a plurality of memory array blocks; a memory addressing circuit capable of addressing said continuously addressable memory space of said semiconductor memory array; a memory operation circuit for performing a memory operation on a selected memory cell within a selected memory array block among said plurality of memory array blocks; and a switching network responsive to said memory addressing circuit for selectively coupling said memory operation circuit to said selected memory cell of said selected memory array block by way of said conductive lines, for performing said memory operation on said selected memory cell.

Abstract: A semiconductor memory array and methods therefor is provided herein comprising a substrate; a plurality of memory cell field effect transistors formed on said substrate and being arranged thereon into rows and columns of transistors, each transistor includes a channel region interposed between drain and source regions, and overlaid by a control gate region; a plurality of first diffused elongated regions formed within said substrate that electrically connect in common the drain regions of transistors in respective columns; a plurality of second diffused elongated regions formed within said substrate that electrically connect in common the source regions of transistors in respective columns; and a plurality of elongated conductive line formed over said substrate that electrically connect in common the control gate regions of transistors in respective rows.

Abstract: A two-dimensional random number generator for use in electronic applications is constructed of a shift-register random number generator using the coefficients of a primitive polynomial of degree k to generate sequences of random binary numbers, and a second random number generator to provide an index to an array of storage locations for storing and retrieving the sequences of random binary numbers generated by the shift-register random number generator.

Abstract: The present invention relates to a signaling system which provides as part of the signal an indication as to the approximate elapsed time since the activation of the signal. Furthermore, the type of service required can be indicated by a particular flashing scheme or color code. The system has both software and hardware components and can be easily integrated into individual game machines. In the preferred embodiment, the hardware component includes a software controllable switching means for controlling a plurality of lights. In order to identify the type of service needed, lights may be color-coded or different flashing patterns may be used. In the software component, a preferred algorithm which defines and varies the flash rate over time is implemented. The flash rate is defined as being in the on-state for a first specified duration and in the off-state for a second specified duration.

Abstract: A rectifying device comprising of a SRMOS, an inductor, and a control circuit is disclosed. The SRMOS has a gate, a drain, and a source. The gate of the SRMOS is connected to the output of the control circuit. The inductor is connected to the drain of the SRMOS. The control circuit uses two sense traces for determining the voltage (or current) passing between the inductor (that is connected to the drain) and the source of the SRMOS. Upon sensing a forward characteristic (voltage or current), the SRMOS forward biases to allow current to flow through the SRMOS. Upon sensing a reverse characteristic (voltage or current), the SRMOS reverse biases to cut off any current flow. Hysteresis is used in setting the forward biasing threshold voltage and the reverse biasing threshold voltage for the SRMOS. In reverse biasing and forward biasing the SRMOS, V.sub.gs is stepped (or curved) controlled to avoid false turn ON/OFF of the SRMOS.

Abstract: A decompression method uses four coefficient inverse perfect reconstruction digital filters. The coefficients of these inverse perfect reconstruction digital filters require a small number of additions to implement thereby enabling rapid decompression in software. The method partially inverse transforms a sub-band decomposition to generate a small low pass component image. This small image is expanded in one dimension by performing interpolation on the rows of the small image and is expanded in a second dimension by replicating rows of the interpolated small image. Transformed chrominance data values may be inverse transformed using inverse perfect reconstruction digital filters having a fewer number of coefficients than the inverse perfect reconstruction digital filters used to inverse transform the corresponding transformed luminance data values.

Abstract: The present invention provides a cooling security system that combines a hardware apparatus with a software routine. The cooling security system detects problems associated with the operation of the fan which is the main component for cooling or heat dissipation, and provides notification of the fan failure to the user via the computer screen. Furthermore, the cooling security system reduces the possibility of overheating by reducing the amount of heat generated by the main heat source, the CPU, by lowering its speed. The present invention also responses to the "GREEN" (Power Down) signal provided by the system board and stops the fan in order to save power.

Abstract: A method for organizing frames of data into queues for prioritized transmission is disclosed. Frames in queues can be transmitted to the other computer systems, and the priority of transfer is set according to the type of data. The frame currently being viewed is provided with a high priority. If the user changes frame before the first frame of data has been completely transmitted, the transmission of the first frame will be suspended and the second frame of data will begin transfer even though the information in the first frame has not been completely transferred. When the transmission of the second frame of data has been completed and if there are no other interruptions, the transmission of the first frame of data will resume. If the user switches back to the first frame of data before the transmission of the second frame is completed, the transmission of the second frame will be suspended and placed in a different priority queue.

Abstract: A memory module using non-standard configuration memory devices while allowing access by computer systems is disclosed. In one example, according to the JEDEC standard 2M.times.36 configuration, the memory module is comprised of two banks of 1M deep memory blocks. For this JEDEC standard configuration, the computer system will provide four Row Address Strobe (RAS) signals, four Column Address Strobe (CAS) signals, a Write Enable signal, and ten address signals, A0-A9. The RAS and CAS signals allow memory blocks of the memory banks to be accessed. However, with only ten address signals, only 1M deep memory devices having 1M deep memory locations can be addressed. In order to use 2M deep memory devices having 2M deep memory locations, an eleventh address signal (A10) is needed. A logic circuit is thus provided to derive an additional address signal and to provide the needed refresh cycle for the second 1M memory locations of the 2M deep memory devices.

Abstract: The present invention in the form of a computer software program provides for a method for annotating over static images or annotating over active application programs. In the case of static images, user-created objects can be created, manipulated and placed over static images. In the case of annotating over application programs in a structured system environment such as in a windows environment, an overlay program embodying the present invention provides an overlaying method allowing the user to switch back and forth between the active application programs and the overlay program. When the overlay program has control, a screen-size, transparent window is created and annotations are created in this window. This transparent window allows the user to see the application programs on the screen. Thus, when creating annotations on this window, a visual perception is created that the annotations are on the images displayed by the application programs.

Abstract: Exponential and pseudo-exponential decay function values are generated by scaling a fractional decrease per sampling period by a previous decay function value and then subtracting the scaled fractional decrease from the previous decay function value. In one embodiment, a multiplier multiplies the fractional decrease by the previous decay function value and provides a product signal representing the scaled fractional decrease. An adder subtracts the scaled fractional decrease from the previous decay function value. In another embodiment, a shift block replaces the multiplier and approximates multiplication by a binary shift of the fractional decrease. The size of the shift is determined by the previous magnitude of the decay function as indicated by a priority encoder. Shifting generates a pseudo-exponential decay function which is suitable for music synthesis and can be generated quickly using less expensive hardware.

Abstract: A video module including a video sensor having a sensor video signal output terminal, a timing signal terminal, and an image field of pixel elements responsive to incident light to generate sensor video signals; a processor having a sensor video signal input terminal coupled to the output terminal, a host signal input terminal for accepting a host signal, a timing signal terminal, video pixel signal combining means responsive to the sensor video signal and the host signals simultaneously to develop display video signals where each of the pixel elements is individually manipulated and controlled, and a display video signal output terminal for outputting the display video signals; a video display having a thin screen disposed along an axis passing through the center of and perpendicular to the image field and facing oppositely from the image field, a display video signal input terminal, and a timing signal terminal, wherein the video signals generate video images on the screen; and a timer for providing timing

Abstract: An expansion card for a personal computer digitizes, optionally processes and/or compresses, stores, and then relays to the personal computer video information without the use of a frame store memory. An analog-to-digital converter on the expansion card digitizes at least part of a frame of an analog video signal received on a video connector of the expansion card. After optional processing and/or compressing of the digitized video information of the frame, part of the digitized video information is stored into a relatively small memory on the expansion card. Once stored, the digitized video information is transferred from the memory and to the personal computer over a parallel bus of the personal computer. Another part of the digitized video information of the frame is then stored into the same memory on the expansion card for subsequent transfer to the personal computer over the parallel bus.

Abstract: A trolling motor system and method for controlling the trolling motor, including a microcontroller, a plurality of transducers, a steering motor, and an outboard motor. The user is allowed to input commands via a keypad and the selected mode of operation is displayed via an LCD screen. The microcontroller operates the transducer to transmit sonar signals and the return signals are received and processed accordingly. In the preferred embodiment, there are five transducers arranged in a manner such that the port (left side of the boat) and starboard (right side of the boat) sides as well as the bottom of the boat are scanned continuously.The microcontroller processes the signals according to the user-selected mode, determines the steering degree and the motor speed, transmits these values to the Steering Motor And Position controller and the Power Drive And Motor controller.

Abstract: A method for testing the timing parameters of a system design is presented, especially suited for use in testing for timing violations between the pins of a semiconductor device. A description of the timing constraints of the various modules of a design is written in a common non-technical vernacular, and functions as an input file. A Timing Shell Generator converts the input file description into a simulator-environment-compatible output code-language file description. The output code-language file is operative to implement the timing constraints of the original input file during simulation such that any violations of the prescribed timing constraints are indicated to the tester who can then take appropriate action.

Abstract: A timing generator contains an oscillator section (10) formed with a plural number of stages (S.sub.1 -S.sub.N) for respectively producing a like number of stage signals (V.sub.S1 -V.sub.SN) that sequentially change signal values at a basic oscillator frequency (f.sub.O). The oscillator section is typically implemented as a ring oscillator. In response to the stage signals, a timing-signal generating section (14) generates one or more timing signals (V.sub.T1 -V.sub.TM), each having at least two transitions corresponding to transitions of two or more of the stage signals. A control section (12), preferably arranged in a phase-locked loop, causes the oscillator frequency and a reference frequency (f.sub.R) to have a substantially fixed relationship.