Patents Represented by Attorney EMPK & Shiloh, LLP
  • Patent number: 7652930
    Abstract: The present invention is a method circuit and system for erasing one or more non-volatile memory (“NVM”) cells in an NVM array. One or more NVM cells of a memory array may be erased using an erase pulse produced by a controller and/or erase pulse source adapted to induce and/or invoke a substantially stable channel current in the one or more NVM cells during an erasure procedure. The voltage profile of an erase pulse may be predefined or the voltage profile of the erase pulse may be dynamically adjusted based on feedback from a current sensor during an erase procedure.
    Type: Grant
    Filed: April 3, 2005
    Date of Patent: January 26, 2010
    Assignee: Saifun Semiconductors Ltd.
    Inventors: Assaf Shappir, Ilan Bloom, Boaz Eitan
  • Patent number: 7638835
    Abstract: An NVM cell such as an NROM cell is formed using a portion of one ONO stack and an adjacent portion of a neighboring NROM stack. A gate structure is formed between (and atop) the two ONO portions, or “strips” (or “stripes”). This provides having two physically separated charge storage regions (nitride “strips”, or “stripes”) in each memory cell.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: December 29, 2009
    Assignee: Saifun Semiconductors Ltd.
    Inventors: Rustom Irani, Boaz Eitan, Ilan Bloom, Assaf Shappir
  • Patent number: 7638850
    Abstract: A method for creating a non-volatile memory array includes implanting pocket implants in a substrate at least between mask columns of a given width and at least through an ONO layer covering the substrate, generating increased-width polysilicon columns from the mask columns, generating bit lines in the substrate at least between the increased-width polysilicon columns and depositing oxide at least between the polysilicon columns.
    Type: Grant
    Filed: May 24, 2006
    Date of Patent: December 29, 2009
    Assignee: Saifun Semiconductors Ltd.
    Inventors: Eli Lusky, Assaf Shappir, Rustom Irani, Boaz Eitan
  • Patent number: 7626732
    Abstract: The disclosure relates generally to the field of printing. More specifically, the disclosure relates to an inspecting process for a printing cylinder.
    Type: Grant
    Filed: October 19, 2006
    Date of Patent: December 1, 2009
    Assignee: Elbit Vision Systems Ltd.
    Inventors: Tsafir Grinberg, Gadi Harpaz, Omri Govrin, Yoram Hasidi, Arkadi Machtei
  • Patent number: 7613232
    Abstract: A method and apparatus for controlling an output power level of a radio frequency (RF) repeater (100 or 200). A system includes a receiver to receive a signal, a filtering unit configured to pass frequency components at or around a frequency band of a predetermined communication channel, an attenuator (124 or 142) to produce an attenuated signal by attenuating a parameter of the signal, a power amplifier (150) to adjust the output power level of repeater to a desired level by adjusting the gain of one or more components of the system, and a microprocessor (170) to receive an input responsive to the output power level of the repeater and, in response to the input, to transfer control signals to the receiver and the attenuator. The method includes sampling traffic load characteristics during operation of a network and adjusting a gain of one or more components of the repeater based on the traffic load characteristics.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: November 3, 2009
    Assignee: Axel Wireless Ltd.
    Inventors: Amir Meir, Alexander Baber, Yaniv Avital
  • Patent number: 7605579
    Abstract: The present invention is a method and apparatus for regulating current consumption and output current of a charge pump. According to some embodiments of the present invention, a first current coming into the charge pump and a second current coming into a driver of at least one of one or more stages of the charge pump is measured. A control loop may regulate one or more parameters of the charge pump and/or a load connected to the charge pump, such as by adjusting one or more of: a supply voltage; a stage's voltage; the stage's frequency and/or duty-cycle; and the number of stages.
    Type: Grant
    Filed: November 21, 2006
    Date of Patent: October 20, 2009
    Assignee: Saifun Semiconductors Ltd.
    Inventors: Yoram Betser, Alexander Kushnarenko, Oleg Dadashev
  • Patent number: 7599227
    Abstract: Methods for minimizing current consumption in a memory array during programming of non-volatile memory cells, such as NROM cells, in the array include: programming a cell without having a direct current flowing from a positive supply to ground through the array, programming a plurality of cells with programming pulses without discharging a global bit line carrying a programming voltage between programming pulses, and programming a cell with transient currents.
    Type: Grant
    Filed: April 14, 2008
    Date of Patent: October 6, 2009
    Assignee: Saifun Semiconductors Ltd.
    Inventor: Eduardo Maayan
  • Patent number: 7590001
    Abstract: In certain exemplary embodiments, a memory device with optimized write sectors has a plurality P of memory write sectors and N memory spare sectors Cumulatively, the memory write sectors correspond to the specified storage capacity of the memory. The number N of spares is approximately equal to the number of write sectors expected to be decommissioned within an operational lifetime of the memory, which can be determined by empirical measurement. A method, by way of non-limiting example, of making memory includes specifying a plurality P of write sectors which define a specified storage capacity of a memory device, determining a number N of spare sectors, and making a memory device with about P write sectors and about N spare sectors. The number N can be determined, by way of example, by summing the infant mortality with the random failure of write sectors.
    Type: Grant
    Filed: December 18, 2007
    Date of Patent: September 15, 2009
    Assignee: Saifun Semiconductors Ltd.
    Inventor: Meir Janai
  • Patent number: 7573745
    Abstract: A die for a memory array may store Flash and EEPROM bits in at least one Nitride Read Only Memory (NROM) array. Each array may store Flash, EEPROM or both types of bits.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: August 11, 2009
    Assignee: Saifun Semiconductors Ltd.
    Inventors: Eduardo Maayan, Boaz Eitan
  • Patent number: 7535765
    Abstract: A non-volatile device and method of operating the device including changing a read reference level for reading a group of memory cells as a function of changes in a threshold voltage distribution of a different group of memory cells. The changing step may include determining a history read reference level of a history cell associated with a group of memory cells of a non-volatile memory cell array and comparing sensed logical state distributions with stored logical state distributions.
    Type: Grant
    Filed: July 10, 2007
    Date of Patent: May 19, 2009
    Assignee: Saifun Semiconductors Ltd.
    Inventor: Eduardo Maayan
  • Patent number: 7532529
    Abstract: A method for sensing a signal received from an array cell within a memory array, the method comprising the steps of generating an analog voltage Vddr proportional to a current of a selected array cell of the memory array, and comparing the analog voltage Vddr with a reference analog voltage Vcomp to generate an output digital signal. A method is also provided for sensing a memory cell by transforming a signal from a memory cell to a time delay, and sensing the memory cell by comparing the time delay to a time delay of a reference cell. Related apparatus is also disclosed.
    Type: Grant
    Filed: August 14, 2006
    Date of Patent: May 12, 2009
    Assignee: Saifun Semiconductors Ltd.
    Inventors: Oleg Dadashev, Yoram Betser, Eduardo Maayan
  • Patent number: 7518908
    Abstract: A method for operating an electrically erasable programmable read only memory (EEPROM) array includes providing an array including a multiplicity of memory cells, wherein each memory cell is connected to a word line and to two bit lines, selecting one of the memory cells, and erasing a bit of the selected memory cell while applying an inhibit word line voltage to a gate of an unselected memory cell. An EEPROM array is also described, the array including a multiplicity of NROM memory cells, wherein each memory cell is connected to a word line and to two bit lines, and wherein each NROM cell is individually erasable and individually programmable without significantly disturbing unselected cells.
    Type: Grant
    Filed: May 28, 2002
    Date of Patent: April 14, 2009
    Assignee: Saifun Semiconductors Ltd.
    Inventors: Eduardo Maayan, Ron Eliyahu, Boaz Eitan
  • Patent number: 7511762
    Abstract: An apparatus for receiving essentially uncompressed HDTV video must generate an accurate pixel-rate clock to enable the reconstruction of a video frame. The clock pixel-rate generated must match a received video pixel-rate. In such system, signals for generation of horizontal and vertical synchronization are not transmitted over the wireless link to conserve the use of bandwidth. In the invention, a start of frame (SOF) indication is extracted by a symbol detection and synchronization (SDS) module and is used to generate the pixel-rate clock.
    Type: Grant
    Filed: September 6, 2006
    Date of Patent: March 31, 2009
    Assignee: Amimon Ltd.
    Inventors: Nathan Elnathan, Shay Freundlich
  • Patent number: 7512009
    Abstract: A method for programming one or more reference cells is described. The reference cell is programmed a predetermined amount, its program state is sensed relative to a prescribed cell on the same die (e.g., a memory cell or a golden bit cell), and the programming process continues until the reference cell fails a preselected read operation. In one preferred embodiment, the memory cell used during the reference cell programming process is the cell in the memory array having the highest native threshold value. In another preferred embodiment, the memory cell used during the reference cell programming process is a native cell that is on-board the die containing the memory array, but not a cell within the memory array.
    Type: Grant
    Filed: April 27, 2006
    Date of Patent: March 31, 2009
    Assignee: Saifun Semiconductors Ltd.
    Inventors: Eduardo Maayan, Ron Eliyahu, Ameet Lann, Boaz Eitan
  • Patent number: 7500483
    Abstract: This invention is a neonatal airway adapter (10) with a sliding internal passage (54), which virtually eliminates void volumes (112) within the bore (76) of the airways, such that mixing of the exhales pages with void gases is reduced, and the waveform of the breath is maintained without undue distortion. Furthermore, the virtual elimination of void volumes reduces the level of re-breathing. The neonatal airway adapter connects to endotracheal tube adapters is such a way as to nullify the effect of the differing internal diameters (20) and internal lengths which are used in ET adapters currently available. The cross section of the internal bore of the airway through which the breath flows from the ET adapter to the connector of the ventilator is maintained almost constant, especially in the region of the gas sampling point (66), to ensure that reasonable conditions of laminar flow, and accurate sampling are maintained.
    Type: Grant
    Filed: May 9, 2005
    Date of Patent: March 10, 2009
    Assignee: Oridion Medical (1987) Ltd.
    Inventors: Lewis Colman, Gershon Levitsky
  • Patent number: 7493051
    Abstract: All-optical system for generating high rate modulated signals. An optical rate increasing device for use with the system includes: an optical loop including an optical amplifier and a gate and having a first terminal and a second terminal coupled to said optical loop, wherein the optical loop is arranged to receive a first periodic signal from the first terminal and to produce therefrom a second periodic signal at the second terminal, and wherein the rate of the second periodic signal is higher than the rate of the first periodic signal.
    Type: Grant
    Filed: January 22, 2008
    Date of Patent: February 17, 2009
    Assignee: Main Street Ventures LLC
    Inventors: Arie Shahar, Eldan Halberthal
  • Patent number: 7489562
    Abstract: A die for a memory array may store Flash and EEPROM bits in at least one Nitride Read Only Memory (NROM) array. Each array may store Flash, EEPROM or both types of bits.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: February 10, 2009
    Assignee: Saifun Semiconductors Ltd.
    Inventors: Eduardo Maayan, Boaz Eitan
  • Patent number: 7488229
    Abstract: Breath test methods and apparatus for increasing accuracy and reducing the time taken to achieve diagnostically useful results. In order to determine when an increase in isotopic ratio of the exhaled breath is clinically significant, methods are described for the use of a variable and multiple threshold level; for reducing the time taken to determine an accurate baseline level; and for avoiding the effects of oral activity when making measurements. To increase measurement accuracy, methods are described, using the results of the breath tests themselves, of continuous and automatic self-calibration to correct for drifts in the gas spectrometer absorption curves. A method for increasing the spectral stability of cold cathode discharge infra-red light sources for use in breath test instrumentation is described. Calibration checking devices and methods of mandating their use at regular time intervals are described, to ensure maintenance of the accuracy of breath tests.
    Type: Grant
    Filed: June 10, 2003
    Date of Patent: February 10, 2009
    Assignee: Oridion Medical (1987) Ltd.
    Inventors: Ilan Ben-Oren, Ephraim Carlebach, Julian Daich, Lewis Colman, Gershon Levitsky, Boaz Givron, Daniel Katzman
  • Patent number: 7479639
    Abstract: System and method for determining an energy window in a medical imaging system. The imaging system, designed to operate in a single photon counting mode, includes a pixilated radiation detector having an array of detector elements coupled to respective electronic channels. The method includes measuring the electronic signals produced for each detector element and producing two spectra corresponding to two different energy levels of photons, deriving an electrical offset for the signals received from each detector element and producing corrected signals and a corrected spectrum of radiation flux impinging on the detector, calculating a peak channel value measured in units of energy channels, and determining an energy window for each detector element such that the width of the window is equal to a desired fraction of the peak channel value.
    Type: Grant
    Filed: August 30, 2007
    Date of Patent: January 20, 2009
    Assignee: Orbotech Medical Solutions Ltd.
    Inventors: Arie Shahar, Uri El-Hanany
  • Patent number: 7468926
    Abstract: A method for erasing memory cells in a memory array, the method including applying an erase pulse to bits of a cell ensemble of a memory cell array, and performing an erase verification operation only on a subgroup of the cell ensemble being erased to check if the memory cells threshold voltage (Vt) has been lowered to an erase verify (EV) voltage level.
    Type: Grant
    Filed: January 19, 2006
    Date of Patent: December 23, 2008
    Assignee: Saifun Semiconductors Ltd.
    Inventors: Assaf Shappir, Shai Eisen