Abstract: An integrated circuit (IC) includes multiple embedded test circuits that all include a ring oscillator coupled to a test load. The test load either is a direct short in the ring oscillator or else is a interconnect load that is representative of one of the interconnect layers in the IC. A model equation is defined for each embedded test circuit, with each model equation specifying the output delay of its associated embedded test circuit as a function of Front End OF the Line (FEOL) and Back End Of the Line (BEOL) parameters. The model equations are then solved for the various FEOL and BEOL parameters as functions of the test circuit output delays. Finally, measured output delay values are substituted in to these parameter equations to generate actual values for the various FEOL and BEOL parameters, thereby allowing any areas of concern to be quickly and accurately identified.

Abstract: A method of estimating a capacitance of each resource in a programmable logic device (PLD) is described. The current drawn by a reference circuit implemented in the PLD is measured at a given frequency and operating voltage. The capacitance of the reference circuit is calculated using the current drawn, the frequency, and the operating voltage. The current drawn by a resource load coupled to the reference circuit is measured at the given frequency and operating voltage. The capacitance of the resource load coupled to the reference circuit is calculated using the current drawn, the frequency, and the operating voltage. The capacitance of the resource load may be calculated by subtracting the capacitance of the reference circuit from the capacitance of the resource load coupled to the reference circuit.

Abstract: A structure and method of performing an analog-to-digital conversion uses a voltage generator which generates an analog reference signal in response to a clock signal. The analog reference signal is a ramp signal which varies between two on-chip supply voltages. A voltage divider circuit receives an analog input signal to be digitized and the analog reference signal. The voltage divider circuit creates an analog control signal equal to the sum of a predetermined fraction of the analog input signal and a predetermined fraction of the analog reference signal. The analog control signal is provided to a first digital buffer and the analog reference signal is provided to a second digital buffer. The first and second digital buffers provide digital control signals having a first logic state when the applied input signal is less than a threshold voltage and having a second logic state when the applied input signal is greater than the threshold voltage.