Abstract: A method and computer program product for predicting quiescent current variation of an integrated circuit die include steps of: (a) receiving as input a system design including a design under timing analysis, an external device, and an interface between the design under timing analysis and the external device; (b) generating a timing model for the external device; and (c) constructing a timing test harness for a static timing analysis tool from the timing model for the external device and the design under timing analysis.

Abstract: A method and apparatus for redirecting void diffusion away from vias in an integrated circuit design includes steps of forming an electrical conductor in a first electrically conductive layer of an integrated circuit design, forming a via between a distal end of the electrical conductor and a second electrically conductive layer of the integrated circuit design, and reducing tensile stress in the electrical conductor to divert void diffusion away from the via.

Abstract: A method of implementing an engineering change order includes steps of: (a) receiving as input an integrated circuit design; (b) receiving as input an engineering change order to the integrated circuit design; (c) creating at least one window in the integrated circuit design that encloses a change to the integrated circuit design introduced by the engineering change order wherein the window is bounded by coordinates that define an area that is less than an entire area of the integrated circuit design; (d) performing a routing of the integrated circuit design that excludes routing of any net that is not enclosed by the window; (e) replacing an area in a copy of the integrated circuit design that is bounded by the coordinates of the window with results of the incremental routing to generate a revised integrated circuit design; and (f) generating as output the revised integrated circuit design.

Abstract: A method and computer program product for verifying an incremental change to an integrated circuit design include receiving as input an integrated circuit design database and an engineering change order. Objects in the integrated circuit design database are identified and marked to indicate a current state of the integrated circuit design database. The engineering change order is applied to the integrated circuit design database, and the integrated circuit design database is analyzed to generate a list of incremental changes to the integrated circuit design database resulting from the engineering change order. Objects in the integrated circuit design database included in the list of incremental changes are identified and marked to distinguish objects in the integrated circuit design database that were changed from the current state. The marked integrated circuit design database distinguishing the objects that were changed from the current state is generated as output.

Abstract: A method and computer program product for optimizing critical path delay in an integrated circuit design include steps of: (a) receiving as input an integrated circuit design; (b) performing a timing/crosstalk analysis to identify each timing critical net in the integrated circuit design; (c) selecting an optimum interconnect configuration for minimizing path delay in each timing critical net; (e) performing a detailed routing that includes the selected optimum interconnect configuration for each timing critical net; and (f) generating as output the detailed routing.

Abstract: A method and computer program are disclosed for floorplanning and cell placement of an integrated circuit architecture that include steps of: (a) receiving as input a design for an integrated circuit architecture that includes a plurality of modules and an internal I/O ring; (b) creating a floorplan to define an area for placing module cells for each module in the plurality of modules wherein for each module that overlaps the internal I/O ring, an area of intersection between the area defined for placing the module cells and an area bounded by a side of the internal I/O ring for which the area of intersection is least is a global minimum for the plurality of modules; and (c) generating as output the floorplan for the integrated circuit architecture.

Abstract: A method and computer program product for finding timing critical nets in an integrated circuit design includes steps of: (a) receiving an integrated circuit design as input; (b) calculating an approximate delay for each net in the integrated circuit design wherein the approximate delay includes an estimate of crosstalk delay; (c) identifying timing critical nets from the calculated delay for each net in the integrated circuit design; (d) calculating a corresponding exact delay for each of the timing critical nets; (e) replacing the approximate delay calculated for each of the timing critical nets with the corresponding exact delay to generate a corrected set of net delays for the integrated circuit design; and (f) generating as output the corrected set of net delays for the integrated circuit design.

Abstract: A method and computer program are disclosed for reducing routing congestion in an integrated circuit design that include steps of: (a) receiving as input a design for an integrated circuit die having an inner metal layer and a top metal layer wherein the design includes electrical constraints of each of a plurality of I/O circuits in the integrated circuit die; (b) selecting a number of vias for a via array to form an electrical connection between the inner metal layer and the top metal layer of the integrated circuit die that connects a solder bump formed on the top metal layer to a corresponding one of the plurality of I/O circuits wherein the number of vias is selected to satisfy the electrical constraints of the corresponding one of the plurality of I/O circuits; and (c) generating as output the number of vias determined for the via array.

Abstract: A footprint based optimal characterization of intellectual property (IP) for more deterministic physical integration. The physical integration characteristics are based upon IP physical integration at an anchor point in a pre-defined IC platform. IP footprint characteristics are identified as fixed, variable or prioritized to each other, and bounding constraints are defined based on a set of characteristics for the IP, the platform characteristics and IC design requirements. The IP is physically synthesized using the bounding constraints. The synthesized IP is tested and the bounding constraints are iteratively modified until the characteristics of the synthesized IP are optimized/captured.

Abstract: A clock distribution network for an integrated circuit includes a clock driver for generating a clock signal having a selected clock frequency, a clock net coupled to the clock driver wherein the clock net has a capacitive reactance, and an inductor coupled to the clock net wherein the inductor has an inductive reactance that is substantially equal to the capacitive reactance of the clock net at the selected clock frequency to minimize clock driver output current.

Abstract: A method includes steps of: (a) providing a wafer on which a film has been deposited; (b) exposing an annular area in an edge exclusion zone of the wafer to radiation having a wavelength suitable for patterning the film in the annular area; and (c) modulating the radiation while exposing the annular area to form a pattern in the film in the annular area.

Abstract: A leak detector for detecting a leak of an electrically conductive fluid m a vessel comprises an electrically conductive wire having a melting temperature less than an internal temperature of the vessel and greater than the external temperature of the vessel. The wire is stitched to a heat resistant fabric to hold the wire in place and to thermally and electrically insulate the wire when no leaking fluid is present. Detector means electrically connected to the wire outputs an electrical signal if the wire is fused by leaking fluid permeating the fabric.

Abstract: A chlorinated hydrocarbon sensor is substituted as a portion of a cone perometer. The sensor includes a titanium casing in which a cylindrical sleeve of beryllium alpha target material is fixed. A rod-shaped americium alpha particle source is disposed within the casing and is moved by an electromagnetic relay into an interacting state in which the beryllium sleeve encases the americium alpha particle source. The interfacing beryllium and americium emit high energy neutrons used to detect the chlorinated hydrocarbons. The emission takes place only when an electromagnetic relay is energized so that cessation of energy will cause a cessation of neutron generation. The rod-shaped alpha particle source will then be withdrawn from the cylindrical beryllium sleeve by a retracting spring. The generated neutrons interact with hydrogen and chlorine in the soil surrounding the sensor to produce characteristic gamma radiation that is detected and measured by a sodium iodide scintillation crystal.