Abstract: A method of routing an integrated circuit package includes receiving as input a placement and routing of at least a portion of an integrated circuit package design, selecting a set of at least three trace segments from the placement and routing that includes at least one inner trace segment routed between two outer trace segments, calculating an inner line function for the inner trace segment that is equally spaced from one of an adjacent line function, an adjacent outer line function, and an adjacent outer trace segment on each side of the inner line function, calculating a pair of end points for the inner line function, and generating as output a new routing that reroutes the inner trace segment collinearly with the inner line function and terminates the inner trace segment by the pair of end points.

Abstract: A method and computer program product for automatically correcting errors in an integrated circuit design includes steps of: (a) performing a physical design validation of an integrated circuit design to verify compliance with a set of design rules; (b) generating a results database of design rule violations detected by the physical design validation; (c) identifying locations in the integrated circuit design from the results database for making design corrections according to a post-processing rule deck so that the locations of the design corrections comply with the set of design rules; and (d) implementing the design corrections in the integrated circuit design.

Abstract: A method of buffer insertion for a tree network in an integrated circuit design includes steps of: (a) receiving as input an integrated circuit design including a tree network; (b) selecting a buffer type available to the integrated circuit design from a cell library that results in a minimum total delay for a predetermined wire length; (c) identifying each candidate leaf node in the tree network that has a required pin-specific target delay; (d) inserting a buffer between each internal node that is traversed by a path from a candidate leaf node to a root node of the tree network and each leaf node that is not a candidate leaf node; (e) creating a buffer sub-tree in the tree network from an upstream internal node for each internal node that is traversed by a path from a candidate leaf node to a root node of the tree network; re-parenting each internal node that is traversed by a path from a candidate leaf node to a root node of the tree network to a new buffer in the buffer sub-tree; and (g) generating as out

Abstract: A circuit for parametric testing of an integrated circuit includes an integrated circuit having a plurality of input buffers and a plurality of XOR gates. The plurality of XOR gates have a first input that is connected to an output of one of the input buffers and having a second input that is connected to an output of a preceding XOR gate to form an XOR logic tree.

Abstract: A method and computer readable storage medium for estimating total path delay in an integrated circuit design include of receiving as input a number of stage delays and stage delay variations constituting a path in an integrated circuit design. A sum of the stage delays, a worst case sum of the stage delay variations, and a root-sum-square of the stage delay variations are calculated. A a value of a weighting function is calculated as a function of the number of stage delays. A a weighted sum of the worst case sum of the stage delay variations and the root-sum-square of the stage delay variations is calculated from the weighting function. The weighted sum is generated as output to estimate total path delay.

Abstract: An underfill includes a base material and a filler material added to the base material wherein the filler material constitutes a selected percentage by weight of the underfill to provide an optimum balance between interfacial die stress and solder bump strain for next generation, Cu, low-K silicon technology.

Abstract: A method and computer program product for parasitic extraction from a previously calculated capacitance solution include steps of: (a) receiving as input a design database for an integrated circuit design; (b) receiving as input a first set of operating conditions and a second set of operating conditions for the integrated circuit design; (c) calculating a first resistance solution and a single capacitance solution from the design database and the first set of operating conditions; (d) performing a parasitic extraction of the first resistance solution and the single capacitance solution to generate a first set of parasitic values; (e) calculating a second resistance solution from the design database and the second set of operating conditions; (f) performing a parasitic extraction of the second resistance solution and the single capacitance solution to generate a second set of parasitic values; and (g) generating as output the first set of parasitic values and the second set of parasitic values.

Abstract: A method of modular exponentiation includes receiving as input a first number, a second number, and a modulus for calculating a residue of a product of the first number times the second number modulo the modulus; partitioning the first number into a selected number of pieces; calculating a first product of one of the pieces times the second number; adding a previous intermediate result to the first product to generate a first sum; shifting the first sum by a selected number of bit positions to generate a second product; and reducing a bit width of the second product to generate an intermediate result wherein the intermediate result has a bit width that is less than a bit width of the second product and has a residue that is identical to a residue of the second product modulo the modulus.

Abstract: A method and computer program for estimating a cell delay for an integrated circuit design include steps of selecting a range of values for cell ramptime and load and a range of values for an additional cell parameter. The values for cell ramptime, load, and the additional cell parameter are arranged in a lookup table. A cell delay is calculated for each combination of cell ramptime, load, and the additional cell parameter for the lookup table.

Abstract: A method of routing an integrated circuit package design includes steps of receiving as input at least a portion of an integrated circuit design including a differential pair of two electrical conductors, calculating a value of length mismatch between the two electrical conductors, calculating an added trace length to compensate for an impedance discontinuity of a shorter one of the two electrical conductors, and extending the shorter one of the two electrical conductors by routing the added trace length entirely inside an area surrounded by a contact pad that electrically terminates the shorter one of the two electrical conductors. The routing for the differential pair with the added trace length is generated as output in the integrated circuit design.

Abstract: A method and computer program product that provide a savings in run time for calculating net delays with cross-talk include steps of providing a coupling capacitance, a net capacitance, and one of a worst case maximum net interconnect delay and a best case minimum net interconnect delay of a net comprising a net cell and a net interconnect in an integrated circuit design; providing a worst case margin multiplier and a best case margin multiplier for the integrated circuit design; calculating a worst case minimum net interconnect delay from the worst case maximum net interconnect delay, the coupling capacitance, the net capacitance, and the worst case margin multiplier when the worst case maximum net interconnect delay is provided; and calculating a best case maximum net interconnect delay from the best case minimum net interconnect delay, the net capacitance, and the best case margin multiplier when the best case minimum net interconnect delay is provided.

Abstract: A method and computer program for screening defects in integrated circuit die includes steps of receiving as input measurements of quiescent current for each die in a sample lot of semiconductor die and generating a test matrix from the quiescent current measurements for each die in the sample lot. A de-mixing matrix is computed from independent component analysis that models passing die in the sample lot. A matrix of sources is generated as a product of the test matrix and the de-mixing matrix. The matrix of sources is normalized to zero mean and unit variance. A statistical limit of the passing die in the sample lot is selected from each of the sources in the normalized matrix of sources to determine a maximum and a minimum quiescent current limit for each of the sources. The maximum and the minimum quiescent current limit for each of the sources is generated as output.

Abstract: A latch based random access memory includes an input data register; an input data buffer coupled to the input data register; a latch array coupled to the input data buffer; and a latch array bypass multiplexer for selecting one of the input data buffer and the latch array in response to a memory scan mode signal to generate a first data output of the latch based random access memory from the input data buffer during logic scan testing and a second data output of the latch based random access memory from the latch array during memory scan testing.

Abstract: A method and computer program product for early physical design validation and identification of texted metal short circuits in an integrated circuit design includes steps of: (a) receiving as input a representation of an integrated circuit design; (b) receiving as input a physical design rule deck that specifies rule checks to be performed on the integrated circuit design; (c) generating a specific rule deck from the physical design rule deck wherein the specific rule deck includes only physical design rules that are specific to one of identifying texted metal short circuits in the integrated circuit design and power distribution and input/output cell placement in the integrated circuit design; and (d) performing a physical design validation on the integrated circuit design from the specific rule deck.

Abstract: A method of automatically analyzing RTL code includes receiving as input RTL code for an integrated circuit design. An RTL platform is selected that incorporates design rules for a vendor of the integrated circuit design. The design rules are displayed from the RTL platform on a graphic user interface. A number of the design rules are selected from the graphic user interface. An analysis is performed in the RTL platform of the RTL code for each of the selected design rules. A result of the analysis is generated as output for each of the selected design rules.

Abstract: A method of generating a schematic driven layout for an integrated circuit design includes steps of: (a) receiving as input a representation of a integrated circuit design comprising a hierarchy of blocks; (b) selecting a block in the hierarchy of blocks that requires a physical design and that contains no missing components; (c) generating a physical design for the selected block so that the selected block is no longer a missing component of any other block; and (d) repeating steps (b) and (c) until a physical design has been generated for each block in the hierarchy of blocks.

Abstract: A method of qualifying a process tool includes steps of: (a) finding a plurality of pre-scan defect locations on a surface of a semiconductor wafer; (b) subjecting the semiconductor wafer to processing by the process tool; (c) finding a plurality of post-scan defect locations on the surface of the semiconductor wafer; and (d) calculating a plurality of defect locations added by the process tool from the pre-scan defect locations and the post-scan defect locations.

Abstract: A comb limiter combiner for frequency-hopped communications includes an input signal coupler for coupling to a receiving antenna and distributing the antenna signal to a bank of input bandpass filters. The input bandpass filters have contiguous passbands that comprise the total receiver bandwidth. Each input bandpass filter is connected to a limiter having a threshold substantially equal to the limiting threshold of the receiver. Each limiter is connected to an output bandpass filter similar to the corresponding input bandpass filter to remove out-of-band intermodulation products generated by the limiter. The bank of output bandpass filters is connected to an output signal coupler for coupling to the front end of the receiver.

Abstract: A method for making a self-aligned FET with an electrically active mask comprises the steps of forming a semiconductor layer on an insulating substrate, forming an electrically nonconductive oxide layer on the semiconductor layer, forming an electrically conductive metal layer on the oxide layer, patterning the metal layer and the oxide layer to form an electrically active gate on semiconductor layer, introducing dopants into the semiconductor layer to form a source region and a drain region masked by the metal gate, and illuminating the source and the drain regions with a pulsed excimer laser having a wavelength from about 150 nm to 350 nm to anneal the source region and the drain region.

Abstract: An eye activity monitor of the present invention integrates multiple eye activity parameters and applies them to alertness models to determine the onset of operator fatigue or drowsiness in real time.