Abstract: Apparatus for sampling a signal parameter of a plurality of data signals is disclosed which comprises a plurality of sources (5) of data signals. Each data signal includes sequential groups of data. Each group of data in all of the data signals has the same fixed predetermined time duration, and includes sequential blocks of data. A plurality of parameter determining circuits (16) are each responsive to a respective one of the data signals, and produce sequential signals (COMPLEXITY) having values representing the signal parameter for each of the sequential blocks of data in the data signal. A plurality of accumulators (31) are each responsive to a respective one of the parameter representative signals, and produce a signal representing the cumulative parameter value of the data signal.

Abstract: A transport stream encoder comprises a plurality of component signal sources. One of the component signals sources is a source of an opportunistic data component signal carrying a block of data having a predetermined size to be transferred within a predetermined period of time. A packet generator is coupled to the plurality of component signal sources, and produces a composite packet stream, partitioned into successive groups containing a plurality of packet slots. A memory stores a plurality of priority lists respectively associated with the plurality of packet slots. Each priority list contains a plurality of entries, and each entry contains data representing a respective one of the plurality of component signal sources. A scheduler is responsive to the entries in the plurality of priority lists and conditions the packet generator to generate a packet for each one of the packet slots.

Abstract: A system of the present invention addresses the difficulty of aligning a reference sync byte at the beginning of a data packet during situations where the system experiences severe problems such as arbitrary resets/restarts or transmission disturbances. Specifically, the sync byte at the beginning of the data packet is automatically aligned with the beginning of a data acquisition interval when data is requested, even when there are arbitrary system resets/restarts. The alignment of the first data packet following a system reset is facilitated by the use of a Start Of Packet flag concurrent with the reference byte, together with a controlled logic network.

Abstract: An MPEG compatible decoder receives encoded, compressed data in the form of image representative pixel blocks. The decoder includes a frame memory (20) for storing reconstructed pixel blocks incident to the decoding process. The previously decompressed data is re-compressed (30) before being written to the memory. Stored decompressed data is decompressed for display (34, 26), or as needed for decoding functions such as motion compensation processing (32, 22). The compression performed before writing data to memory is block-based compression using compressed data from one of two different compression paths (FIG. 3, 314, 320) which compress a given pixel block simultaneously.

Abstract: A method is disclosed for decompressing in-place an adjusted monotone compressed file having a first portion containing compression codewords and a second portion containing plain text, into a decompressed file having a size and containing plain text. The method comprising the following steps. First, a memory buffer is allocated having the size of the decompressed file. Then the adjusted monotone compressed file is stored in the bottom of the buffer. Finally, the compression codewords in the first portion of the adjusted monotone compressed file are decompressed to produce plain text of a corresponding portion of the decompressed file in the top of the buffer. A method is also disclosed for compressing a source file into an adjusted monotone compressed file. The method comprises the following steps. First, the source file is monotone compressed into a compressed file containing compression codewords.

Abstract: A system for dynamically allocating a resource is disclosed which includes a plurality of resource users and a resource having a maximum utilization level sharable among the plurality of resource users. A plurality of need analyzers, associated with respective resource users, dynamically generate respective signals (COMPLEXITY), each representing the relative need for the resource by the associated resource user. A plurality of access controllers, associated with respective resource users, control access to the resource by the associated user in response to an allocation signal (CONTROL). A resource allocator dynamically generates allocation signals (CONTROL), representing allocated resource utilization levels for associated users, in response to the plurality of need representative signals (COMPLEXITY) from the need analyzers.

Abstract: The invention relates to a digital processing circuit comprising an analog/digital converter (1) situated at the input of the circuit, a device (2) for the digital processing of the signal emanating from the analog/digital converter and a digital/analog converter (3) situated at the output of the processing circuit. The digital processing circuit comprises means (A2, A3, T, RS, R1) making it possible to control its gain from a single voltage reference (VB). Preferably, the single voltage reference is a bandgap voltage and the circuit is made in CMOS technology. The invention applies to any type of audio or video equipment using such circuits.

Abstract: A television signal receiver for processing an HDTV signal transmitted in a vestigial sideband (VSB) format with a one dimensional data constellation includes a first carrier recovery network (18), an equalizer (20), and a second carrier recovery network (22, 30, 62). A multiple stage quantizer network (50, 66) exhibiting progressively finer resolution is associated with the operation of the equalizer for providing blind equalization without need of a "training" signal. The second carrier recovery network includes a phase detector (30) wherein a one symbol delayed (312) input signal and a quantized (310) input signal are multiplied (316), and an unquantized input signal and a quantized (310) one symbol delayed (314) input signal are multiplied (318). Signals produced by the multiplication are subtractively combined (320) to produce an output signal representing a carrier phase error.

Abstract: A transmission processor (16) receives an input packetized datastream (FIGS. 6-9; FIGS. 15-18 signal A) containing packets of data bytes including MPEG coded video information. The transmission processor outputs a symbol datastream (FIGS. 15-18 signal F) representing a sequence of data fields (FIG. 1) comprising groups of data segments (X) with an associated field sync segment. The transmission processor inserts overhead information. e.g., FEC error coding information, into each data segment, and inserts the longer duration field sync overhead segment between groups of data field segments. The frequency of the transmission processor input byte clock (SC/2, FIG. 6; FIG. 15) an integer sub-multiple of an output symbol clock (SC) frequency. The input datastream exhibits constant uniform inter-packet data gaps and a constant uniform data rate, thereby facilitating the seamless insertion of the field sync overhead segment into the datastream without interrupting the datastream.

Abstract: A television receiver with an MPEG decoder is configurable for full high definition decoding and display, or reduced cost lower definition display. The MPEG decoder (10-33) uses a controllable dual-mode data reduction network selectively employing horizontal detail reduction (29) and data re-compression (30) between the decoder and the decoder frame memory (20) from which image information to be displayed (27) is derived. The amount of data reduction is manufacturer selected in accordance with the resolution of the display device, e.g., equal to or less than high definition resolution. The frame memory size is also manufacturer selected in accordance with the resolution of the display device.

Abstract: A procedure for quantification of coefficients in a variable data rate image compression system, in the form of blocks and macroblocks, the system including circuitry for transformation of blocks of pixels into blocks of coefficients, circuitry for quantification of these coefficients, circuitry for storage of coded information before transmission, and circuitry for regulation of quantification as a function of the state of the circuitry for storage.

Abstract: A distributed computer system, as for transmitting and receiving executable multimedia applications, includes a source of a continuous data stream repetitively transfering data representing a distributed computing application and a client computer, receiving the data stream, for extracting the distributed computing application representative data from the data stream, and executing the extracted distributed computing application.

Abstract: A television receiver with an MPEG decoder is configurable for full high definition decoding and display, or reduced cost lower definition display. The MPEG decoder (10-33) uses a controllable dual-mode data reduction network selectively employing horizontal detail reduction (29) and data re-compression (30) between the decoder and the decoder frame memory (20) from which image information to be displayed (27) is derived. The amount of data reduction is manufacturer selected in accordance with the resolution of the display device, e.g., equal to or less than high definition resolution. The frame memory size is also manufacturer selected in accordance with the resolution of the display device.

Abstract: A television signal receiver for processing an HDTV signal transmitted in a vestigial sideband (VSB) format includes input complex filters shared by a timing recovery network (30) and a carrier recovery network (50). The filter network includes a pair of upper and lower band edge filters (20, 22) mirror imaged around the upper and lower band edges of the VSB signal for producing suppressed subcarrier AM output signals. The timing recovery network includes a phase detector (28, 38, 62) and responds to an AM signal derived from the two filters (via 26) for synchronizing a system clock (CLK). The carrier recovery network (50) also includes a phase detector (54, 60, 62, 64), and responds to outputs from one or both of the filters for producing an output error signal (.DELTA.) representing a phase/frequency offset of the VSB signal. The error signal is used to reduce or eliminate the offset to produce a recovered baseband or near baseband signal.

Abstract: Apparatus in a receiver, for processing transmitted entitlement control information, includes a packet transport processor for selecting signal packets having payloads containing a conditional access payload header and a remaining payload of entitlement data. Respective payload headers include groups of bytes which are coded in a manner to allow or disallow the respective receiver from processing the entitlement data. A conditional access filter preprogrammed with a subscriber specific conditional access codeword examines respective byte groupings of the conditional access header for a match with the subscriber specific conditional access codeword. Only if a match occurs is the processor permitted to process the entitlement data. The entitlement data is thereafter utilized to generate decryption keys for descrambling portions of the transmitted signal.

Abstract: A display device having a plurality of select lines includes redundant select line scanners. Each scanner includes a plurality of substantially identical stages having an input terminal and an output terminal. The stages and select lines are ordinally numbered and correspondingly numbered stages are connected to opposite ends of the correspondingly numbered select lines by separate line segments. The stages within each scanner are cascaded by connecting the output terminal of each stage to the input terminal of the immediately succeeding stage. Failed stages of a scanner are replaced by the correspondingly numbered stage of the other scanner simply by opening the separate line segment of the failed stage.

Abstract: In a digital television signal processing system, a special codeword, a Packet Alignment Flag (PAF), is inserted into an MPEG codeword bitstream to signify the presence of a Group of Pictures (GOP). The PAF immediately precedes a Picture Start codeword for an "I" frame, which initiates a GOP. A data packet under construction when a PAF appears is terminated since a GOP is intended to begin at a packet boundary. Such termination may result in an abbreviated packet of MPEG codewords less than a prescribed number of bits needed to complete a data packet. The last word of each packet is designated as such to facilitate the subsequent combining of data packets with respective headers. An incomplete data packet is filled with null (zeroed bits) words to make up a complete data packet with a prescribed number of bits.

Abstract: A multimode scan converter includes a delay element for delaying one horizontal line of video signal and selectively redisplaying that line. A multiplexer is arranged to selectively provide either luminance signal or chrominance signal to the delay element. Output signal from the delay element and output signal from the multiplexer are coupled to a proportioning circuit which sums the two signals in complementary proportions (e.g. K and 1-K). A second multiplexer, which provides up-converted output luminance signal, is arranged to selectively pass the luminance signal or signal from the proportioning circuit. A third multiplexer, which provides up-converted output chrominance signal, is arranged to selectively pass the chrominance signal or signal from the proportioning circuit.

Abstract: In a digital television signal processing system, a special codeword, a Packet Alignment Flag (PAF (14), is inserted into an MPEG codeword bitstream to signify the presence of a Group of Pictures (GOP). The PAF immediately precedes a Picture Start codeword for an "I" frame, which initiates a GOP. A data packet (12) under construction when a PAF (14) appears is terminated since a GOP is intended to begin at a packet boundary. Such termination may result in an abbreviated packet of less than a prescribed number of codewords needed to complete a data packet. The last word of each packet is designated as such to facilitate the subsequent combining of data packets (12) with respective headers (18). An incomplete data packet is filled with null (zeroed bits) words to make up a complete data packet with a prescribed number of words.

Abstract: A packet encoder includes various sources of data, a state machine and additional circuitry. The state machine provides an S-bit output signal. N of the output bits of the state machine, (N<S), are coupled to directly control a multiplexer without an intervening state decoder. The multiplexer combines data from the various sources into a packet signal.