Abstract: Method for multithread processing of a packet is described. A packet recognition thread is initiated responsive to receiving the packet to a port triggering a media access control (“MAC”) recognition thread. A network protocol recognition thread is activated responsive to the MAC recognition thread for an initiating an address lookup thread and a MAC write thread. The MAC recognition thread, the network protocol thread, the address lookup thread and the MAC write thread all may complete their respective executions prior to completion of the packet recognition thread, thereby reducing latency in packet handling.

Abstract: Method and apparatus for providing a controlled voltage to an integrated circuit is described. A first frequency value indicative of a first voltage is compared to a second frequency value indicative of a second voltage. The second frequency value is adjusted by the second voltage until the second frequency value is within a range of the first frequency value. Additionally, the second voltage may be adjusted to maintain the second frequency value within the range.

Abstract: Method and apparatus are described for providing memory cells enhanced for resistance to single event upsets. In one embodiment, transistors are coupled between cross coupled inverters of a latch, thus in a small area providing both single-event-upset resistivity most of the time, and high speed during writing to the memory cell. Alternatively, inductors coupled between inverters of a latch may be used.