Abstract: An oscillator circuit. In one embodiment, the oscillator includes a gain circuit, an envelope detector, and an amplitude comparison circuit. The trans-conductance circuit is configured to amplify a periodic signal produced by a crystal. Amplitude peaks of the periodic signal may be detected in the envelope detector, which may determine an average amplitude value based on the detected peaks. The average amplitude value may be compared to a DC voltage value in an amplitude comparison circuit. The DC voltage value may include both a DC average of the periodic signal as well as a predetermined DC offset value. The gain circuit may adjust the level of amplification of the periodic signal based on a feedback signal in order to ensure that the oscillator produces a periodic output signal at a desired level so as to insure oscillation and the minimum use of current to achieve oscillations.

Abstract: A method for constructing a capacitor having an increased equivalent series resistance (ESR) is disclosed. In one embodiment, a capacitor includes a plurality of capacitor plates comprised of a conductive material and first and second capacitor terminals. At least one of the capacitor plates is coupled to the first terminal and at least one of the capacitor plates is coupled to the second terminal. At least one of the plurality of capacitor plates includes a pattern, wherein the pattern is void of conductive material. The void in the conductive material formed by the pattern may cause a path of current flow through the capacitor plate to be substantially altered in comparison to a capacitor plate that is continuous. By using capacitor plates having voids of conductive material that cause the current path to be altered in comparison to continuous capacitor plates, a capacitor can be constructed having a higher ESR.

Abstract: A system and method for distributing power to an integrated circuit. In one embodiment, a power laminate may be mounted to a printed circuit board (PCB). The integrated circuit for which power is to be distributed may be electrically coupled to the PCB. The power laminate may include one or more power planes and one or more reference (i.e. ground) planes, with each pair of power/reference planes separated by a dielectric layer. The power laminate may also include a connector or other means for receiving power from an external power source. The power laminate may be electrically coupled to the integrated circuit, thereby enabling it to provide power to the integrated circuit. The power laminate may also include a voltage regulator circuit, and a plurality of decoupling capacitors.

Abstract: A system and method for distributing power to an integrated circuit. In one embodiment, a power laminate may be mounted to a printed circuit board (PCB). The integrated circuit for which power is to be distributed may be electrically coupled to the PCB. The power laminate may include one or more power planes and one or more reference (i.e. ground) planes, with each pair of power/reference planes separated by a dielectric layer. The power laminate may also include a connector or other means for receiving power from an external power source. The power laminate may be electrically coupled to the integrated circuit, thereby enabling it to provide core power to the integrated circuit. The power laminate may also include a voltage regulator circuit, and a plurality of decoupling capacitors. In one embodiment, the power laminate may include a plurality of apertures which allow for the passing of connections between the integrated circuit and the PCB.

Abstract: A system and method for monitoring and controlling a power-manageable resource. In one embodiment, a power manageable resource, such as a bus in a computer system, may be shareable among a number of power-manageable devices. A resource monitor may also be coupled to the power-manageable resource. The resource monitor may be configured to monitor the devices coupled to the power manageable resource. More specifically, the functions of the resource monitor may include monitoring the active/inactive state of each of the attached devices. The resource monitor may be configured to cause the sharable resource to be powered down if it is determined that all the attached devices are in an inactive state.

Abstract: A method and apparatus to ensure DLL locking at a minimum delay is provided. In one embodiment, a DLL circuit includes a phase detector, a counter, a programmable delay line, and a counter control circuit. Upon initialization of the DLL circuit, the counter control circuit is configured to cause the counter to count increment, regardless of the phase relationship between a reference clock signal and the output clock signal. The counter continues incrementing, thereby changing the phase relationship between the reference clock signal and the output clock signal by adjusting the delay of the programmable delay line. This eventually results in a phase lock between the reference clock signal and the output clock signal at a minimum delay. Once the DLL achieves a phase lock between the reference clock signal and the output clock signal, the counter increments or decrements its count in order to maintain or re-acquire a lock.

Abstract: A system and method for bus arbitration. A computer system includes one or more buses for transferring data. Access to each bus is controlled by an arbitration unit. Various bus agents (i.e. peripherals) are coupled to the bus. Some bus agents are designated as normal-priority agents, while other bus agents are designated as high-priority bus agents. A high-priority bus agent may be a peripheral that is a latency-sensitive device. The arbitration unit may grant bus access to a normal-priority bus agent based on an arbitration scheme. When a high-priority bus agent requests access to the bus, the arbitration unit may cause the termination of access by the normal-priority bus agent. The high-priority bus agent is then granted access to the bus. When the high-priority bus agent has completed its use of the bus, the arbitration unit allows the normal-priority bus agent to regain access to the bus.

Abstract: A method and apparatus to ensure DLL locking at a minimum delay is provided. In one embodiment, a DLL circuit includes a phase detector, a counter, a programmable delay line, and a counter control circuit. Upon initialization of the DLL circuit, the counter control circuit is configured to cause the counter to count increment, regardless of the phase relationship between a reference clock signal and the output clock signal. The counter continues incrementing, thereby changing the phase relationship between the reference clock signal and the output clock signal by adjusting the delay of the programmable delay line. This eventually results in a phase lock between the reference clock signal and the output clock signal at a minimum delay. Once the DLL achieves a phase lock between the reference clock signal and the output clock signal, the counter increments or decrements its count in order to maintain or re-acquire a lock.