Abstract: A novel capacitor design and construction method that uses a stacked structure which is sometimes otherwise used for a so-called floating gate transistor. A first electrical contact is electrically coupled with a conductive region formed in the substrate and with a control gate layer. A second electrical contact is electrically coupled with a floating gate layer, forming a plate between the substrate and control gate layers. The footprint of this capacitor is reduced by using both sides of the floating gate layer as capacitive plate. Parasitic capacitance is relatively reduced. One or more dielectric layers can be formed for both capacitors and for floating gate transistors on the substrate in the same process step or steps.

Abstract: A memory cell having an asymmetric source and drain connection to virtual ground bit-lines. A main diffusion, adjacent the drain and displaced from the source, allows Fowler-Nordheim (FN) tunneling erasure on the drain side of the floating gate. A pocket diffusion, between the main diffusion and the source, concentrates the electric field and thereby enhances the efficiency of programming by electron injection on the source side of the floating gate. A nonvolatile semiconductor memory device comprising row and column arrangement of the cells, in which adjacent columns of cells share a single virtual ground bit line.

Abstract: Two crystal oscillators are configured as a "plug-and-play" precision transmit-receive clock that requires no calibration during manufacture. A first crystal oscillator generates a transmit clock and a second crystal oscillator operates at a small offset from a harmonic of the first oscillator. A turnstile circuit selects pulses from the second oscillator to trigger a receive clock. Both the transmit and receive clocks operate at the same frequency. One edge of the receive clock is smoothly slipped, or swept, in phase across a limited range such as 0 to 36 degrees relative to the transmit clock with the slip rate set by the harmonic frequency offset. In one embodiment, a quadrature frequency-locked-loop is used to accurately control the slip rate while preventing false frequency locks. This timebase can be used to clock equivalent time radar, laser, and TDR ranging systems with picosecond accuracy.