Abstract: Apparatus and methods are disclosed for performing time-reversed scheduling of a data dependency graph representing a target program instruction loop in an optimizing compiler. The instruction scheduling function is the modulo scheduling function of an optimizing compiler and it is noted that the time-reverse transforms preserve all modulo constraints. Most modern microprocessors have the ability to issue multiple instructions in one clock cycle and/or possess multiple pipelined functional units and typically contain multi-level memory devices such as on-chip cache, off-chip cache as well as main memory. For such microprocessors this invention can, where applicable, accelerate the process of modulo-scheduling loops in the target program code. The invention consists of a technique to transform the data dependency graph of the target program instruction loop in order to produce an improved schedule of the loop instructions.
Abstract: In its various embodiments, the present invention provides a method and apparatus for creating a target executable program from the source code of a target computer program for execution on a target processor. The target processor provided by the method and apparatus has a first set of registers and a second set of registers. Generally, the target processor is capable of executing a first set of instructions which only address the first set of registers. The method and apparatus provides a second set of instruction for the target processor which include a subset of frequently executed instructions within the first set of instructions. These second set of instructions are novel because they able to address both the first set of registers and the second set of registers. A compiler is provided and used for compiling the source code into a number of target executable instructions and allocating the registers on the target processor.
Abstract: Apparatus and methods are disclosed for scheduling target program instructions during the code optimization pass of an optimizing compiler. Most modern microprocessors have the ability to issue multiple instructions in one clock cycle and/or possess multiple pipelined functional units. They also have the ability to add two values to form the address within memory load and store instructions. In such microprocessors this invention can, where applicable, accelerate the execution of modulo-scheduled loops. The invention consists of a technique to achieve this speed up by systematically reducing the number of certain overhead instructions in modulo scheduled loops. The technique involves identifying reducible overhead instructions, scheduling the balance of the instructions with normal modulo scheduling procedures and then judiciously inserting no more than three copies of the reducible instructions into the schedule.
Type:
Grant
Filed:
November 17, 1995
Date of Patent:
November 10, 1998
Assignee:
Sun Microsystems, Inc.
Inventors:
Partha P. Tirumalai, Krishna Subramanian, Boris Baylin
Abstract: The present invention is a system and method for "checking the use of synchronization locks in a multi-threaded computer program" (hereinafter "WARLOCK II"). In Warlock II a set of source code representing a process which includes multiple threads may be annotated by the developer using a "NOTE" macro to describe the desired operation of the locks. This annotated source code is passed to a modified ANSI C compiler which outputs a special file designated a ".ll" file, as for example, file "foo.ll". This special ".ll" file is then processed as input along with other designated ".ll" files which might be related, by a "wlanalyze" program which will check the source code of the target programs in the ".ll" files to determine whether their use of synchronization locks is consistent with the intended use as specified in the annotations.
Type:
Grant
Filed:
June 9, 1995
Date of Patent:
October 13, 1998
Assignee:
Sun Microsystem, Inc.
Inventors:
Nicholas A. Sterling, Steven R. Kleiman, Charles E. Fineman, Douglas E. Walls, Keith H. Bierman
Abstract: Apparatus and methods are disclosed for determining a recurrence minimum iteration interval (rmii) vector for use in modulo scheduling target program instructions during the code optimization pass of an optimizing compiler. Most modem microprocessors have the ability to issue multiple instructions in one clock cycle and/or possess multiple pipelined functional units. They also have the ability to add two values to form the address within memory load and store instructions. For such microprocessors this invention can, where applicable, accelerate the process of modulo-scheduling target program loops. The invention consists of a technique to determine a rmii vector, which is a set of rmii values which correspond to different values of instruction load latency. The disclosed invention makes the determination of the entire vector with only minimal effort over determining a single rmii value.
Abstract: The present invention provides an elegant and simple way to provide mechanisms for invocation of objects by client applications and for argument passing between client applications and object implementations, without the client application or the operating system knowing the details of how these mechanisms work. Moreover, these mechanisms functions in a distributed computer environment with similar ease and efficiency, where client applications may be on one computer node and object implementations on another. The invention includes a new type of object, termed a "spring object," which includes a method table, a subcontract mechanism and a data structure which represents the subcontract's local private state.
Type:
Grant
Filed:
November 18, 1996
Date of Patent:
July 28, 1998
Assignee:
Sun Microsystems, Inc.
Inventors:
Graham Hamilton, Michael L. Powell, James G. Mitchell, Jonathan J. Gibbons
Abstract: This disclosure describes a solution to this basic problem of transaction management for systems which use the object metaphor to define the interfaces between different components of a system. An elegant solution is described which defines a transaction manager protocol and process, which is independent of the operating system micro-kernel's interprocess communication activities. The object-oriented transaction manager ("TM") creates transactions, keeps track of all object managers (servers) that are a part of a transaction, and coordinates transaction termination among all objects that are involved in the transaction. In addition, operations by naive applications can be made to execute under transaction control without modifying the applications.
Abstract: Apparatus, methods, systems and computer program products are disclosed to provide a hypertext user with a history facility for displaying accessed hypernodes. The invention displays the history list to the user based on when the hypernode was accessed and based on the placement of the hypernode in the hyperlink hierarchy.
Abstract: This Continuation-In-Part describes a part of this run-time debugger operation which is designated the "Fix-and-Continue" invention. This invention permits a user to begin a debugging session wherein if an error in the code is encountered, the user can edit the corresponding source code to correct the error and then execute a "Fix and Continue" command all without leaving the debugging session. The Fix and Continue code calls the compiler to recompile the source code file with the edited text in it, receives the resulting recompiled object code file from the compiler, uses the dynamic linker to link the recompiled object code into the target application program process, patches the previous version of this same object code fie to refer to the newly recompiled code, resets any required variables and registers, resets the program counter to the line of code being executed when the error was discovered.
Type:
Grant
Filed:
September 1, 1994
Date of Patent:
October 7, 1997
Assignee:
Sun Microsystems, Inc.
Inventors:
Thomas Preisler, Wayne C. Gramlich, Eduardo Pelegri-Llopart, Terrence C. Miller
Abstract: The present invention provides an economical, high performance, adaptable system and method for a type-specific data presentation by a development tool. In the preferred embodiment, one or more type-specific function name are found from the symbol table of the target program which might be able to display a data object. These type-specific function names are analyzed to determine if one and only one such name is able to display the data object and if so the found function name is used to call that function to display the data object. In the preferred embodiment the development tool is a debugger for C++ target programs.
Type:
Grant
Filed:
July 7, 1995
Date of Patent:
October 7, 1997
Assignee:
Sun Microsystems, Inc.
Inventors:
Crispin S. Perdue, David W. Weatherford, Thomas Preisler
Abstract: The present invention provides a system and process which has the advantages of shortening the time and cost required to create a new localized version of a software product by automating much of the language translation process; by providing tools to automate the modifications to the program being localized, thereby reducing the probability of creating errors in the localization process and providing some measure of consistency between subsequently localized new releases of the product, and between different locales. The system disclosed includes an environment and tools to develop software modules to create methods to display, enter or print various single and multi-byte character sets. Moreover the system disclosed provides a mechanism for an independent software developer to localize a software product, using only a binary copy of the target program and the localization tool kit for that product.
Type:
Grant
Filed:
March 17, 1995
Date of Patent:
September 2, 1997
Assignee:
Sun Microsystems, Inc.
Inventors:
Jaime Murow, Gary D. Hethcoat, Richard J. Kwan, Hideki Hiura