Abstract: A cathode for electrolytic processes, particularly suitable for hydrogen evolution in chlor-alkali electrolysis comprises a metal substrate provided with a catalytic coating made of two layers containing palladium, rare earths (such as praseodymium) and a noble component selected between platinum and ruthenium. The rare earth percent amount by weight is lower in the outer layer than in the inner layer.
Type:
Grant
Filed:
April 5, 2012
Date of Patent:
November 20, 2012
Assignee:
Industrie de Nora S.p.A.
Inventors:
Antonio Lorenzo Antozzi, Alice Calderara, Marianna Brichese
Abstract: A time delay circuit is disclosed and includes a delay line with a first delay circuit and at least a second delay circuit connected downstream. An interpolation circuit is used to generate intermediate signals derived by delayed successive signals in the delay line.
Type:
Grant
Filed:
January 29, 2009
Date of Patent:
March 30, 2010
Assignee:
Infineon Technologies AG
Inventors:
Stephan Henzler, Siegmar Köppe, Dominik Lorenz
Abstract: A method of forming at least a portion of a dual bit memory core array upon a semiconductor substrate, the method comprising performing front end processing, performing a first bitline implant, or pocket implants, or both into the first bitline spacings to establish buried first bitlines within the substrate, depositing a layer of the spacer material over the charge trapping dielectric and the polysilicon layer features, forming a sidewall spacer adjacent to the charge trapping dielectric and the polysilicon layer features to define second bitline spacings between adjacent memory cells, performing a deep arsenic implant into the second bitline spacings to establish a second bitline within the structure that is deeper than the first bit line, removing the sidewall spacers and performing back end processing.
Type:
Grant
Filed:
December 26, 2006
Date of Patent:
March 2, 2010
Assignee:
Spansion LLC
Inventors:
Timothy Thurgate, Yi He, Ming-Sang Kwan, Zhizheng Liu, Xuguang Wang
Abstract: A magnetic scanner employs constant magnetic fields to mitigate zero field effects. The scanner includes an upper pole piece and a lower pole piece that generate an oscillatory time varying magnetic field across a path of an ion beam and deflect the ion beam in a scan direction. A set of entrance magnets are positioned about an entrance of the scanner and generate a constant entrance magnetic field across the path of the ion beam. A set of exit magnets are positioned about an exit of the scanner and generate a constant exit magnetic field across the path of the ion beam.
Type:
Grant
Filed:
September 19, 2006
Date of Patent:
November 10, 2009
Assignee:
Axcelis Technologies, Inc.
Inventors:
Bo H. Vanderberg, Robert D. Rathmell, Edward C. Eisner
Abstract: A circuit for amplifying an input voltage (VIN) into an output voltage (VOUT) with an overall gain factor, which is a product of a first gain factor (S) and a second gain factor (R1), comprises means for generating an intermediate signal (I2) from the input voltage (VIN) and the first gain factor (S) and means for generating the output voltage (VOUT) from the intermediate signal (I2) and the second gain factor (R1). The first gain factor (S) and the second gain factor (R1) have opposite temperature dependencies.