Abstract: The inductance of an inductor is increased by forming a conductive wire to have a serpentine shape that weaves through a ferromagnetic core that has a number of segments that are connected together in a serpentine shape where each segment of the ferromagnetic core also has a number of sections that are connected together in a serpentine shape.

Abstract: A system and method is disclosed for calibrating a semiconductor wafer handling robot and a semiconductor wafer cassette. A robot blade boot is attached to a robot blade of the semiconductor handling robot. The robot blade boot decreases a value of tolerance for the robot blade to move between two semiconductor wafers in the semiconductor wafer cassette. In one embodiment the vertical tolerance is decreased to approximately twenty thousandths of an inch (0.020?) on a top and a bottom of the robot blade boot. The use of the robot blade boot makes the calibration steps more critical and precise. The robot blade boot is removed from the robot blade after the calibration process has been completed.

Abstract: A copper-topped interconnect structure allows the combination of high density design areas, which have low current requirements that can be met with tightly packed thin and narrow copper traces, and low density design areas, which have high current requirements that can be met with more widely spaced thick and wide copper traces, on the same chip.

Abstract: Method and system for adaptive signal equalizing with alternating boost and amplitude controls. In accordance with one exemplary embodiment, data signal boost control is based on measured equalized and sliced data signal energies within a bandwidth disposed about a higher frequency, while sliced data signal amplitude control is based on measured equalized and sliced data signal energies within a bandwidth disposed about a lower frequency.

Abstract: A method includes forming first isolation trenches in a first side of a first semiconductor-on-insulator (SOI) structure to electrically isolate multiple portions of the first SOI structure from each other. The method also includes bonding a second SOI structure to the first SOI structure to form multiple cavities between the SOI structures. The method further includes forming conductive plugs through a second side of the first SOI structure and forming second isolation trenches in the second side of the first SOI structure around the conductive plugs. In addition, the method includes removing portions of the second SOI structure to leave a membrane bonded to the first SOI structure. The isolated portions of the first SOI structure, the cavities, and the membrane form multiple capacitive micromachined ultrasonic transducer (CMUT) elements. Each CMUT element is formed in one of the isolated portions of the first SOI structure and includes multiple CMUT cells.

Abstract: A controlled seam magnetic core lamination utilizable in an inductor structure includes a magnetic base and first and second spaced-apart magnetic sidewalls extending substantially orthogonally from the base to define a seam therebetween.

Abstract: A Group III-N high electron mobility transistor is driven by a high-voltage gate driver that limits the gate-to-source voltage across the transistor by controlling the maximum charge that can be placed on a boot strap capacitor that charges up the gate of the transistor to turn on the transistor.

Abstract: A self-propelled robotic device moves through bodily and other passageways by inflating regions of an overlying bladder along the length of the robotic device in a sequence that imparts motion to the device. The regions of the overlying bladder are inflated by energizing a plurality of coils, which are surrounded by a ferrofluid, in a sequence. The ferrofluid responds to the magnetic field created by an energized coil by creating a bulge in the side wall of the overlying bladder.

Abstract: In a SOI process, a high voltage BJT structure with BVCEO versus FT control is provided by including a bias shield over the laterally extending collector region and controlling the bias of the shield.

Abstract: A metal interconnect structure, which includes a bond pad, an overlying anti-reflective coating layer, an overlying passivation layer, and an opening that exposes a top surface of the bond pad, eliminates corrosion resulting from the anti-reflective layer being exposed to moisture during reliability testing by utilizing a side wall spacer in the opening that touches the side wall of the passivation layer, the side wall of the anti-reflective coating layer, and the top surface of the bond pad.

Abstract: An integrated circuit package configured to incorporate a lead frame and methods for its making are is described. The package comprising an IC with aluminum bond pads in communication with circuitry of the die with lead frame with silver bond pads. The package having gold bumps bonded between the aluminum bond pad of the die and the silver bond pad of the lead frame. The package including an encapsulant envelope and including various materials and bond pad structures and constructed in a manner formed by thermosonically or thermocompressionally bonding the gold balls to the bond pads. Also, disclosed are methods of making the package.

Abstract: A memory cell includes a control gate and a transistor having a gate, a source junction, and a drain junction. The gate is coupled to the control gate, and the source junction and the drain junction are asymmetrical. For example, a channel doping associated with the source junction may be different than a channel doping associated with the drain junction. The memory cell also includes a write line coupled to the control gate, a source line coupled to the source junction of the transistor, and a bit line coupled to the drain junction of the transistor. The control gate could represent a second transistor, where the gates of the transistors are coupled together to form a floating gate. The memory cell could be programmed to store a single-bit value or a multiple-bit value, such as by storing the appropriate charge on the floating gate.

Abstract: A method includes forming a transistor device on a first side of a semiconductor-on-insulator structure. The semiconductor-on-insulator structure includes a substrate, a dielectric layer, and a buried layer between the substrate and the dielectric layer. The method also includes forming a conductive plug through the semiconductor-on-insulator structure. The conductive plug is in electrical connection with the transistor device. The method further includes forming a field plate on a second side of the semiconductor-on-insulator structure, where the field plate is in electrical connection with the conductive plug. The transistor device could have a breakdown voltage of at least 600V, and the field plate could extend along at least 40% of a length of the transistor device.

Abstract: A copper-compatible fuse target is fabricated by forming a target structure at the same time that a trace structure is formed on a passivation layer, followed by the formation of an overlying non-conductive structure. After the overlying non-conductive structure has been formed, a passivation opening is formed in the non-conductive structure to expose the passivation layer and the side wall of the target structure.

Abstract: System and method for adaptive signal equalizing in which overlapping data signal equalization paths provide cumulative data signal equalization to provide multiple equalized data signals having different available amounts of equalization. Signal slicing circuitry slices the equalized data signals to provide multiple sliced data signals, from which the sliced data signal selected as an output data signal is dependent upon the data rate of the incoming data signal.

Abstract: A method is provided for enhancing charge storage in an E2PROM cell structure that includes a read transistor having spaced apart source an drain diffusion regions formed in a semiconductor substrate to define a substrate channel region therebetween, a conductive charge storage element formed over the substrate channel region and separated therefrom by gate dielectric material, a conductive control gate that is separated from the charge storage element by intervening dielectric material, and a conductive heating element disposed in proximity to the charge storage element. The method comprises performing a programming operation that causes charge to be placed on the charge storage element and, during the programming operation, heating the heating element to a temperature such that heat is provided to the charge storage element.

Abstract: A system and method is disclosed for providing a low voltage high density multi-bit storage flash memory. A dual bit memory cell of the invention comprises a substrate having a common source, a first drain and first channel, and a second drain and a second channel. A common control gate is located above the source. A first floating gate and a second floating gate are located on opposite sides of the control gate. Each floating gate is formed with a sharp tip adjacent to the control gate and an upper curved surface that follows a contour of the surface of the control gate. The sharp tips of the floating gates efficiently discharge electrons into the control gate when the memory cell is erased. The curved surfaces increase capacitor coupling between the control gate and the floating gates.

Abstract: A digital control loop within power switchers and the like includes a sliding error sampler pulse width modulation timing variably setting a number of clock cycles relative to a digital pulse width modulator output trailing edge for loading control variables for a filter. A computation time for the proportional-integral-derivative filter is predicted based on an average for previous digital pulse width modulator outputs, computed within the integral path for the previous loop iteration. A margin is added to accommodate transient conditions accelerating the trailing edge of the digital pulse width modulator output, either fixed or variable depending on the previous iteration pulse width.

Abstract: In a silicon-based light emitting diode-photodiode (LED-PD) arrangement, the LED is implemented as an avalanche LED (ALED) and the ALED and PD are integrated into a common integrated circuit. The ALED is formed around a cross-shaped PD and is separated from the PD by a deep trench region. In order to create current crowding close to the deep trench the ALED includes an NBL or PBL having a narrowing at its end.

Abstract: Apparatuses and methods directed to a semiconductor chip package having multiple leadframes are disclosed. Packages can include a first leadframe having a die attach pad and a first plurality of electrical leads, a second leadframe that is generally parallel to the first leadframe and having a second plurality of electrical leads, and a plurality of direct electrical connectors between the first and second leadframes, where such direct electrical connectors control the distance between the leadframes. Additional device components can include a primary die, an encapsulant, a secondary die, an inductor and/or a capacitor. The plurality of direct electrical connectors can comprise polymer balls having solder disposed thereabout. Alternatively, the direct electrical connectors can comprise metal tabs that extend from one leadframe to the other. The first and second leadframes can be substantially stacked atop one another, and one or both leadframes can be leadless leadframes.