Abstract: Provided is a semiconductor structure that comprises a substrate; a conductor; and insulating layer separating the conductor from the substrate; and a removable conductive strap coupled to the conductor and the substrate for maintaining a common voltage between the conductor and substrate during ion beam and/or plasma processing; and a method for fabricating.

Abstract: A method and apparatus for handling an electrostatic discharge (ESD) pulse in silicon on insulator (SOI) integrated circuits is provided. An ESD pulse is conducted via an ESD protection circuit from a pad to a rail or node. A discriminator means coupled to the rail or node determines when an ESD pulse has occurred and generates a signal in response thereto. The signal from the discriminator means is applied to a body bias circuit.

Abstract: The invention comprises an input/output circuit of an integrated circuit chip that includes a pad, a protection circuit connected to the pad, and an up-shift circuit connected to the pad and the protection circuit. The up-shift circuit provides a DC bias voltage to signals received by the pad to protect the protection circuit. With the invention, the protection circuit includes only single gate-oxide devices.

Abstract: The present invention provides an integrated circuit which comprises a substrate having a plurality of device regions formed therein, said plurality of device regions being electrically isolated from each other by shallow trench isolation (STI) regions and said plurality of device regions each having opposing edges abutting its corresponding STI region; selected ones of said devices regions having a preselected first device width such that an oxide layer formed thereon includes substantially thicker perimeter regions, along said opposing edges, compared to a thinner central region that does not abut its corresponding STI region; and selected other ones of the device regions having a preselected device width substantially narrower in width than the first device width such that an oxide layer formed thereon includes perimeter regions, along opposing edges, that abut each other over its central region thereby preventing formation of a corresponding thinner central region.

Abstract: A pair of dynamic random access memory cells having each end of the active area surrounded on three sides by a gate conductor. The width of each end of the active area that is surrounded by a gate conductor preferably is less than fifty percent of the width of the deep trench intersected by that end of the active area.

Abstract: A device, having circuits formed thereon, comprises a circuit including a frequency generator for generating a detectable radio frequency energy when powered and a power generator, coupled to the frequency generator, for generating power when exposed to light.

Abstract: A system and method for testing the most complex portions of transceiver devices integrated into digital VLSI chips. The testing is performed in a manufacturing environment with minimal external hardware and using a combination of test-specific circuitry and pattern algorithms built into a mixed signal transceiver implementing a test methodology suitable for application and measurement on a digital tester.

Abstract: A logic circuit device and circuit design methodology includes a “split-book” logic circuit design having different active device sizes with outputs for connections to both critical and non-critical digital circuit paths. By using “split” book designs with separate input and output stages, better silicon utilization, power optimization, and performance results. This is because each split book is designed with multiple output buffers that may be configured to optimally drive critical and non-critical paths. During the power/performance optimization phase of the design, timing critical paths of the design are first identified, with each path being optimized on its own basis. First the input stage of the strand may be improved with a stronger drive on the input port of the book. Only the input port that has been linked to a critical path is updated. The other input pins are left at their default setting.

Abstract: A structure and method for processing data comprises a processing unit having a base cache, base registers having a base width and being operatively connected to the processing unit, and virtual cache registers having a virtual width and being located in the base cache and operatively connected to the processing unit, wherein a base processing precision of the processing system is determined by the base width of the base registers and a selectable enhanced processing precision is determined by the virtual width of the virtual cache registers, wherein the base registers store base instructions and data and the virtual cache registers store enhanced data, the virtual width being greater than the base width, and wherein the base cache includes tags identifying a portion of the base cache as the virtual registers, the virtual cache registers being accessible by the processing unit only for execution of enhanced instructions for providing the enhanced processing precision.

Abstract: A device design for an FET in SOI CMOS which is designed for enhanced avalanche multiplication of current through the device when the FET is on, and to remove the body charge when the FET is off. The FET has an electrically floating body and is substantially electrically isolated from the substrate. The present invention provides a high resistance path coupling the floating body of the FET to the source of the FET, such that the resistor enables the device to act as a floating body for active switching purposes and as a grounded body in a standby mode to reduce leakage current. The high resistance path has a resistance of at least 1 M-ohm, and comprises a polysilicon resistor which is fabricated by using a split polysilicon process in which a buried contact mask opens a hole in a first polysilicon layer to allow a second polysilicon layer to contact the substrate.

Abstract: A system and method for measuring hysteresis effects of a wafer process. The method comprises steps of generating a pulse having a pulse width equal to the delay of a transition through a delay chain wherein the delay chain has been in a static condition for a substantial length of time; counting a number of oscillations from a ring oscillator generated during the pulse width wherein the ring oscillator has been operating in a steady state condition; comparing the number of oscillations with an expected value; and correlating a difference resulting from the comparing step with a level of hysteresis effected by the wafer process.

Abstract: A microprocessor for a portable computer, for reducing power consumption, includes a plurality of microcode units, the microcode units for outputting control signals, for each of a plurality of instructions, requires by the microprocessor for executing the instructions. A unit is provided for maintaining selected control signals to values the same as in an immediately previous instruction cycles. Further, there is a unit for passing a control variable to one of the microcode units. Power conservation is provided during the decoding of instructions by the microcode unit by maintaining control signals during the execution of an instruction at the values/levels determined during the decode of a preceding instruction if it is not necessary to change the level of the control signals to execute the instruction.

Abstract: A high voltage tolerant diode structure for mixed-voltage, and mixed signal and analog/digital applications. The preferred silicon diode includes a polysilicon gate structure on at least one dielectric film layer on a semiconductor (silicon) layer or body. A well or an implanted area is formed in a bulk semiconductor substrate or in a surface silicon layer on an SOI wafer. Voltage applied to the polysilicon gate film, electrically depletes it, reducing voltage stress across the dielectric film. An intrinsic polysilicon film may be counter-doped, implanted with a low doped implantation, implanted with a low doped source/drain implant, or with a low doped MOSFET LDD or extension implant. Alternatively, a block mask may be formed over the gate structure when defining the depleted-polysilicon gate silicon diode to form low series resistance diode implants, preventing over-doping the film.

Abstract: A MOSFET device and a method of manufacturing the device. The device has a trench formed in a silicon substrate. The channel of the device is at the bottom of the trench. Diffusion layers are formed adjacent to opposite sides of the trench. Each diffusion layer is connected to the edge of the device channel by extending the diffusion layer along the side wall of the trench and under a portion of the trench.

Abstract: An integrated circuit chip comprises a plurality of clock distribution sub-networks each including a clock input for receiving a clock signal, each of the clock distribution sub-networks having a capacitance, as seen from the clock input, substantially equivalent to others of the clock distribution sub-networks; and a structured clock buffer having a size based on a load of the clock distribution sub-networks, and providing the clock signal to the clock distribution sub-networks.

Abstract: A DC offset cancellation circuit receives two input signals. A first one of the input signals is amplified by an amplifier, and the amplified output signal of the amplifier is tracked and held during a first clock phase. Simultaneously, during the first clock phase, the second one of the input signals is tracked and held. During the second clock phase succeeding the first clock phase, the stored second one of the input signals is amplified by the same amplifier that was used to amplify the first one of the input signals. The amplified and stored first one of the input signals and the amplified second one of the input signals are summed during the second clock phase to remove any DC offset. The summed signals are sampled and held during the second clock phase. The offset of the summer circuit can be canceled by sequential digital processing.

Abstract: A circuit for selectively controlling the slew rate of a signal on a data line. A capacitor is connected at one end to a common terminal of a power supply and to a switching circuit. The switching circuit advantageously connects the capacitor to the data line in response to a control pulse, capacitively loading the data line so that slew rate is decreased. When the control pulse assumes a different state, the capacitor is connected by the switching circuit to a terminal of a power supply, and acts as a decoupling capacitor. The dual role of the capacitor provides for efficient circuit layout by utilizing one component in two functions.

Abstract: The present invention provides a method for fabricating an integrated circuit (IC) structure having an Al contact in electrical communication with Cu wiring embedded in the initial semiconductor wafer. In accordance with the method of the present invention, the Al contact is formed in areas of the IC structure which contain or do not contain an underlying region of Cu wiring. The present invention also provides a method of interconnecting the fabricated structure to a semiconducting packaging material through the use of a wirebond or Controlled Collapse Chip Connection (C4) solder.

Abstract: A method for doping a poly depleted semiconductor transistor, the semiconductor transistor including a gate region, a source region adjacent the gate region and a drain region adjacent the gate region and opposite the source region, the method comprising steps of exposing the gate region to a first ion implantation and shielding the gate region from a second ion implantation step.