Abstract: A surface-emitting light-emitting diode having increased light emission is provided.

Abstract: A 2T-1C FRAM, each cell of which includes two transistors and one ferroelectric capacitor so that the “charging” and “discharging” of the ferroelectric capacitor used in conjunction with the p-n junction of the two transistors performs write/read operations without switching thereby avoiding degradation problems such as fatigue and imprint in the 2T-1C FRAM.

Abstract: A method for fabricating a MOS transistor using a selective silicide process wherein a gate insulating layer and a gate polysilicon layer are sequentially formed on a silicon substrate, and a gate spacer is formed on a side wall of the gate insulating layer and the gate polysilicon layer. Impurity ions are implanted and diffused using the gate spacer and the gate polysilicon layer as a mask layer to form a source/drain region in the substrate. An etching blocking layer is formed to cover the source/drain region, the gate spacer, and the gate polysilicon layer, and then, a dielectric layer to cover the etching blocking layer is formed. The dielectric layer is planarized, and the etching blocking layer on the gate polysilicon layer is exposed. The exposed etching blocking layer and a part of the gate spacer are etched, and a top surface and a top side of the gate polysilicon layer are exposed. A silicide layer is formed over the exposed part of the gate polysilicon layer.

Abstract: An improved capacitor for a semiconductor memory device for preventing a bridge between storage electrodes and enlarging a surface area of a capacitor can be manufactured by forming a second insulating layer on a first insulating layer including a plug, etching the second insulating layer to form a storage electrode opening by using a storage electrode formation mask until the plug and a part of the first insulating layer are exposed, forming a conductive spacer on the sidewalls of the storage electrode opening to connect electrically to the plug, and forming an HSG (hemispherical grain) layer on the surfaces of the conductive spacers and the plug. A capacitor according to the present invention enables the HSG layer to grow on an internal wall of a storage electrode, thereby preventing a micro-bridge between storage electrodes resulting from abnormal growth or over-growth of the HSG layer.

Abstract: A semiconductor device having a fuse includes a first insulating layer that has a predetermined metal wire, a second insulating layer that has a heat blocking layer being positioned over the predetermined metal wire, and an upper layer. The upper layer includes a deposition structure having a fuse metal layer and a wiring metal layer. The fuse metal layer has a fuse pattern that is used as a fuse and is exposed via a fuse window in the upper layer. The fuse pattern is electrically connected to the wiring metal layer. The semiconductor device is designed so that the heat blocking layer is larger than the fuse window and is positioned under the fuse metal layer. The semiconductor device is further constructed with the fuse metal layer being formed on the metal wire, thereby preventing limitations in the layout arrangement or in the fabrication process in order to achieve a high degree of integration. A method of manufacturing the above semiconductor device is also described.

Abstract: A light-emitting polymer is represented by the following formula (I): wherein R1, R2 and R3 are selected from the group consisting of linear aliphatic alkyl groups, branched alkyl groups and fluorinated alkyl groups. Light-emitting copolymers formed by copolymerizing units of formula (I) with MEH-PPV (methoxyethylhexyloxy-PPV) are also provided.

Abstract: A storage electrode structure and method of manufacturing thereof. Storage electrodes of dummy cells arranged in a word line direction and a bit line direction at the peripheral regions of a cell are formed such that every two or three dummy cells in a word line direction are formed in a single pattern. As a result, the loading effect produced in the peripheral regions of the cell region is reduced. The invention also reduces short-circuit bridging caused by collapsing storage electrode patterns in the dummy cells since the storage electrodes are not connected together. Accordingly, it is possible to minimize an increase in the loading capacitance of bit lines when an electrical short circuit occurs between a bit line and an associated buried contact.

Abstract: A semiconductor device having a double layer type anti-reflective layer, which can reduce reflectivity in a photolithography process using, for example, an exposure light source of a 193 nm wavelength region and which can suppress intermixing at the boundary between an anti-reflective layer and a photoresist layer, and a fabrication method of the semiconductor device are disclosed. The semiconductor device includes an underlying layer having a high reflectivity formed on a semiconductor substrate, a double layer type anti-reflective layer formed of a nitride layer and a layer formed using only hydrocarbon-based gas on the underlying layer, and a photoresist layer formed on the double layer type anti-reflective layer. In the double layer type anti-reflective layer, the nitride layer and the layer formed using only hydrocarbon-based gas can be sequentially stacked. Also, it is possible that the layer formed using only hydrocarbon-based gas and the nitride layer are sequentially stacked.

Abstract: A six-axes force-moment measuring apparatus includes a mechanical structure having sensors installed at predetermined positions on the mechanical structure for measuring tensile and compressive forces applied to each axis. The output signal from the sensors is processed and analyzed to determine the forces and/or moments applied to the mechanical structure. The six-axes force-moment measuring apparatus is readily constructed and repaired, and is capable of supporting large loads.

Abstract: A non-volatile semiconductor device and a method of making such a device having a memory cell formation part and a peripheral circuit part having high and low-voltage transistor formation parts, wherein the device includes an anti-punch through region surrounding a drain region in the memory cell formation part, and surrounding drain and source regions of the low-voltage transistor formation part.

Abstract: A process for preparing an 1,3-alkanediol through carbonylation of an epoxide derivative includes the steps of (a) reacting an epoxide derivative with alcohol and carbon monoxide in a solvent at a temperature from about 30 to about 150° C. and at a pressure from about 50 to about 3000 psig in the presence of a catalyst system including an effective amount of a cobalt catalyst and an effective amount of a promoter to afford a reaction mixture including a 3-hydroxyester or derivative thereof in an amount of from 2 to about 95% by weight, (b) separating the reaction product and solvent from the catalyst and promoter, (c) reacting said reaction product and solvent with hydrogen at a temperature from about 30 to about 350° C. and at a pressure from about 50 to about 5000 psig in the presence of a catalyst system for hydrogenation to prepare a hydrogenation product mixture including a 1,3-alkanediol, and (d) recovering the 1,3-alkanediol from the hydrogenation product mixture.

Abstract: An LED lamp apparatus comprises a plurality of LED lamps including at least one LED chip mounted on a printed circuit board, on which a driver circuit and/or a control circuit are provided in a printed circuit pattern to drive and/or control the LED chip, at least one female lead electrode terminal constituted as a hollow coupling pin to be inserted into at least one through holes for at least one power source terminal and a control signal tenninal and a body made into a unit of the LED lamp, using transparent or translucent epoxy resin, in which the LED lamps are arranged in series or parallel to form a predetermined block, the driver and control circuits are respectively or collectively provided in the block, and one block or a plurality of blocks arranged in series or parallel are made into a body to be molded into transparent or translucent epoxy resin to form a case.

Abstract: A method for fabricating a semiconductor device, wherein a dual damascene metal line is formed utilising a material layer pattern. The material layer pattern has openings to define contact holes both for metal interconnection in the peripheral region and for storage nodes in the cell array region. The material layer pattern is formed on an insulating layer. A second insulating layer is deposited on the material layer pattern. A groove mask pattern is formed and used as an etch stop while etching through the etching is performed at the another insulating layer and stopped at the material layer to form a first opening. Using the material layer pattern, exposed portions of the insulating layer are etched to form a second opening aligned to the first opening and thereby to form a dual damascene opening for a metal line. Metal is deposited in the first and second opening to form dual damascene metal lines.

Abstract: A ferroelectric capacitor with a multilayer ferroelectric film to prevent degradation of its ferromagnetic characteristics, wherein the ferroelectric film is made of a lower layer of PZT or PLZT formed on a lower electrode and an upper, titanium rich, layer of PZT, PLZT, or PbTiO3, an upper electrode formed on the upper layer of the ferroelectric film and a protective layer formed to cover the ferroelectric capacitor.

Abstract: A self aligned contact (SAC) pad in a semiconductor device and a method for forming thereof wherein an SAC opening is formed concurrently with single-layer gate spacers. After formation of the stacked gate pattern having a gate electrode and a capping layer disposed thereon, an insulating layer for gate spacers is deposited thereon. An interlayer insulating layer then is deposited over the insulating layer. The interlayer insulating layer has an etch selectivity with respect to the capping layer and insulating layer. SAC then are opened in the interlayer insulating layer while concurrently forming single-layer gate spacers.

Abstract: A dielectric layer is formed by depositing a first dielectric layer above a semiconductor substrate including recessed regions, etching the first dielectric layer to remove any voids and to lower the aspect ratio of the recessed regions, and depositing a second dielectric layer on the first dielectric layer in the recessed regions. The method is particularly useful when the aspect ratios are high for recessed regions formed between patterns.

Abstract: A first conductive impurity ion is implanted into a semiconductor substrate to form a well area on which a gate electrode is formed. A first non-conductive impurity is implanted into the well area on both sides of the gate electrode to control a substrate defect therein and to form a first precipitate area to a first depth. A second conductive impurity ion is implanted into the well area on both sides of the gate electrode, so that a source/drain area is formed to a second depth being relatively shallower than the first depth. A second non-conductive impurity is implanted into the source/drain area so as to control a substrate defect therein and to form a second precipitate area. As a result, substrate defects such as dislocation, extended defect, and stacking fault are isolated from a P-N junction area, thereby forming a stable P-N junction.

Abstract: A metallization process for manufacturing semiconductor devices and a system that uses the same that minimizes corrosion failures in aluminum patterns. The process for the metal pattern formation is carried out by loading a semiconductor wafer into an etching chamber, the semiconductor wafer having a photoresist pattern formed over a metal material layer, stabilizing the environment in the etching chamber, main-etching the metal material layer to the etch-end point by using the photoresist pattern as an etch mask while supplying etching gas containing chlorine (Cl2) into the etching chamber, over-etching the metal material layer for a certain period of time over the etch-end point so as to form metal patterns, purging the etching chamber after the over-etching step, and unloading the wafer from the etching chamber. The pressure in the transfer module is optimized, and the load lock chamber is continuously purged.

Abstract: A method of compensating a phase error of a phase encoding gradient pulse in fast spin echo (FSE) imaging, wherein a bipolar type phase encoding gradient pulses for tuning are applied between a 90° RF signal and a first 180° RF signal in a FSE sequence to obtain a tuning value. Alternatively, an additional 180° RF signal is applied between a 90° RF signal and a first 180° RF signal in a FSE sequence, and then phase encoding gradient pulses for tuning are applied between the additional 180° RF signal and the first 180° RF signal to obtain a tuning value. The phase errors of the phase encoding gradient pulses are compensated for using the obtained tuning value. Accordingly, a ringing artifact or blurring phenomenon of an image can be reduced in the FSE imaging, and the contrast of an image can be improved.

Abstract: A chemical mechanical polishing apparatus includes a polishing pad, a wafer carrier, a first ring, a second ring, a pad conditioning unit and at least one cleaning solution supply pipe. The first ring surrounds the semiconductor wafer and the edge of the wafer carrier. The second ring surrounds the first ring. The cleaning solution supply pipes are connected to the second ring and/or to the pad conditioning unit to supply the cleaning solution into the gaps between the rings, the wafer carrier and portions of the pad conditioning unit to remove solidified slurry from the gaps.