Abstract: A composition for sustained release comprises a carrier material containing a non-polymeric, non-water soluble liquid material having a viscosity of at least 5,000 cP at 37° C. that does not crytallize neat under ambient physiological conditions, a multivalent metal cation, and growth hormone.

Abstract: A method of making a semiconductor structure comprises forming a hole through a first dielectric layer; followed by forming a hole through an etch-stop layer, to expose a first conducting layer. The thickness of the etch-stop layer is at least one-half the smallest line width of the first conducting layer.

Abstract: A method of making a semiconductor structure includes trimming a patterned hard mask with a wet etch, wherein the hard mask is on a gate layer; and etching the gate layer. In making multiple structures on a semiconductor wafer, an average width of lines in the patterned hard mask is trimmed by at least 100 ?.

Abstract: A method of forming a semiconductor structure comprises forming an etch-stop layer comprising nitride, on a stack. The stack is on a semiconductor substrate, and the stack comprises (i) a gate layer. The forming is by CVD with a gas comprising a first compound which is SixL2x, and a second compound comprising nitrogen and deuterium, L is an amino group, and X is 1 or 2.

Abstract: A method is described for forming a trench in a semiconductor substrate, which has a silicon layer, an oxide layer overlying the silicon layer, and a nitride layer overlying the oxide layer. The method includes etching the nitride layer to a nitride end point using a nitride etching chemistry, which includes a fluorinated hydrocarbon, oxygen, and an inert gas selected from the group consisting of neon, argon, krypton, xenon, and combinations thereof. Methods of making semiconductor devices, methods of reducing defects in semiconductor devices, and silicon wafers having trenches and isolation regions formed by the above-mentioned methods for forming a trench are also described.

Abstract: Prior to etching a poly-II layer during fabrication of an integrated circuit, a hydrofluoric acid (HF) dip is used to remove surface oxides from the poly-silicon layer and an anisotropic descumming operation is used to remove any resist material left over from a patterning operation. Following patterning, a long breakthrough etch (e.g., sufficient to remove 300-1500 ? of oxide) using an anisotropic breakthrough etchant (e.g., a fluorocarbon-based etchant) is performed before the poly-silicon layer is etched. The HF dip may be repeated if a predetermined time between the first dip and the etch is exceeded. The anisotropic descumming operation may be performed using an anisotropic anti-reflective coating (ARC) etch, e.g., a Cl2/O2, HBr/O2, CF4/O2 or another etch having an etch rate of approximately 3000 ?/min for approximately 10-20 seconds. The poly-silicon layer may be annealed following (but not prior to) the etch thereof.

Abstract: A novel biosensor comprises at least one fluorophore and at least two quenchers, and is capable of selectively and specifically detecting the presence of an ion in the presence of other ions.

Abstract: A method of making a structure, includes filling a via hole with a conductive material, to form a via. The via hole passes through an etch-stop opening. In both directions along a first axis dielectric material is present between the via hole and edges of the etch-stop layer, and in both directions along a second axis, perpendicular to said first axis, dielectric material is not present between the via hole and edges of the etch-stop layer.

Abstract: A composite material, contains a polymer, a polymerizer, a corresponding catalyst for the polymerizer, and a plurality of capsules. The polymerizer is in the capsules. The composite material is self-healing.

Abstract: A method of making a semiconductor structure includes determining a polish time which is sufficient to planarize a layer on a semiconductor substrate. The layer is polished for the polish time to planarize the layer, and then the layer is polished to a predetermined thickness. The semiconductor structures can be used to make a semiconductor device.

Abstract: A process for fabricating a semiconductor structure comprises depositing a nitride layer on a semiconductor substrate with a first tool, and depositing an anti-reflective layer on the semiconductor substrate with the first tool. The nitride layer includes silicon and nitrogen.

Abstract: A method of forming a semiconductor structure is described that includes etching a trench in a semiconductor substrate, wherein an oxide layer overlies the semiconductor substrate, and a nitride layer overlies the oxide layer; and cleaning the semiconductor substrate while simultaneously performing a pull back of the nitride layer. Methods of making semiconductor devices and electronic devices, and silicon wafers having trenches and isolation regions formed by the above-mentioned methods are also described.

Abstract: A mask simulation process is introduced into a conventional OPC procedure, prior to simulation of a photoresist pattern. Reticle simulation may be achieved using very short wavelengths of light as compared to the mask feature size. Alternatively, reticle simulation may be made through adjustments in a computer aided design process.

Abstract: A method of making a semiconductor structure includes sealing a gate layer by wet oxidation. The gate layer is on a substrate containing isolation regions. Semiconductor devices prepared from the semiconductor structure exhibits reduced inverse narrow width effects.

Abstract: A method of forming a semiconductor structure comprises forming a nitride layer on a stack, and etching the nitride layer to form spacers in contact with sides of the stack. The stack is on a semiconductor substrate, the stack comprises (i) a gate layer, comprising silicon, (ii) a metallic layer, on the gate layer, and (iii) an etch-stop layer, on the metallic layer. The forming is by CVD with a gas comprising SixL2x, L is an amino group, and X is 1 or 2.

Abstract: An assembly for holding a substrate is provided. The substrate has a first surface, a second surface, opposite the first surface and an outer peripheral portion. The assembly includes a holding body having a support surface for supporting the substrate. The holding body has an aperture for passing therethrough a gas having a thermal conductivity. Additionally, the assembly includes a heat transferring seal having a first surface for frictionally engaging the second surface of the substrate. The heat transferring seal has a second surface, opposite the first surface, for frictionally engaging the support surface of the holding body. The heat transferring seal also has an inner peripheral portion defining an opening for receiving the gas. The heat transferring seal has a thermal conductivity closely matched with the first thermal conductivity of the gas for providing substantially uniform heat transfer across the substrate.

Abstract: A process for minimizing lateral spacer erosion of an insulating layer adjacent to a contact region and an apparatus whereby there is provided a contact opening with a small alignment tolerance relative to a gate electrode or other structure are disclosed. The process includes the steps of forming a conductive layer on a semiconductor body, then depositing an insulating layer adjacent to the conductive layer. Next, substantially rectangular insulating spacers are formed adjacent to the gate electrode. An etch stop layer is deposited adjacent the insulating layer, followed by an etch to remove the etch stop layer material from the contact region. This etch is conducted under conditions wherein the etch removes the etch stop layer, but retains the substantially rectangular lateral spacer profile of the first insulating layer.

Abstract: A semiconductor structure including a semiconductor substrate, an isolation trench in the semiconductor substrate, and an alignment trench in the semiconductor substrate is disclosed. The structure also includes a dielectric layer and a metallic layer. The dielectric layer is on the semiconductor substrate and in both the isolation trench and the alignment trench. The dielectric layer fills the isolation trench and does not fill the alignment trench. The metallic layer is on the dielectric layer.

Abstract: A method of forming a semiconductor structure is described that includes etching a first metal layer at the bottom of a via in a first insulating layer to expose a second metal layer, wherein the first metal layer is on the second metal layer, and wherein the etching of the first metal layer is not reactive-ion etching. Methods of making semiconductor devices and electronic devices are also described.