Abstract: A transient recovery circuit for switching devices. The transient recovery circuit includes a detecting circuit for detecting a rapid transient in an output voltage of a switching device by detecting a rate of the output voltage transient; an auxiliary controlling circuit in a feedback loop of the switching device for correcting the output voltage by changing a bandwidth of the feedback loop if the rapid transient is detected; and an initializing circuit for initializing the feedback loop to expected operating points in a continuous conduction mode after correcting the output voltage.

Abstract: Efficient switch cascode architecture for switching devices, such as switching regulators. The cascode architecture includes a switching stage responsive to an external driver signal for switching transitions, and a bias generator operative to bias the cascode transistor of the switching stage to protect the switching stage from damage during the switching transitions.

Abstract: A method includes identifying a first syllable in a first audio of a first word and a second syllable in a second audio of a second word, the first syllable having a first set of properties and the second syllable having a second set of properties; detecting the first syllable in a first instance of the first word in an audio file, the first syllable in the first instance having a third set of properties; determining one or more transformations for transforming the first set of properties to the third set of properties; applying the one or more transformations to the second set of properties of the second syllable to yield a transformed second syllable; and replacing the first syllable in the first instance of the first word with the transformed second syllable in the audio file.

Abstract: An example of a circuit for generating high-voltage switching at an output terminal of the circuit includes a pair of n-type metal oxide semiconductor (NMOS) transistors responsive to input signals to generate a first voltage signal in a preset mode. The circuit also includes a predefined number of n-type cascode stages coupled between the output terminal and the pair of NMOS transistors to enable propagation of the first voltage signal to the output terminal. Further, the circuit includes a predefined number of p-type cascode stages coupled to the output terminal to enable propagation of the first voltage signal to an input voltage supply to the circuit. Furthermore, the circuit includes a first pair of cross-coupled p-type metal oxide semiconductor (PMOS) transistors coupled to the input voltage supply. The circuit includes a pair of PMOS transistors, coupled between the first pair of cross-coupled PMOS transistors and the p-type cascode stage.

Abstract: Online batch processing. A job request is received from a user for processing. The job request includes a job configuration and a plurality of operations to process the data. The job configuration is extracted from the job request and stored in a configuration cache. A metadata configuration code is extracted from the job configuration and stored in a code cache. A runtime configuration code is extracted from the job configuration and stored in an instance cache. This allows information to be obtained from the configuration cache, the code cache and the instance cache for processing subsequent job requests with the similar job configuration and the plurality of operations. The data is fetched from at least one of the job request and an external storage device. The plurality of operations is executed on the data to generate a result. The result is provided to the user through at least one of an output stream and the external storage device.

Abstract: Power up circuit. An example power up circuit includes a switch for charging a power node of an electronic device. A level detector is used for monitoring charge level of the power node. Further, the power up circuit includes one or more power switches for providing current to the electronic device based on the charge level.

Abstract: A method and system for efficient processing of structured documents is provided. The method includes creating fragments of the structured document. The method also includes creating an ordered list including a plurality of descriptors pointing to the structured document fragments. Further, the method includes modifying the ordered list for manipulating of the structured document. The system includes one or more message blocks. The system also includes a message control block for pointing to the one or more message blocks. Further, the system includes one or more data blocks and a plurality of binary tokens for pointing to the one or more data blocks. Moreover, the system includes a plurality of ordered lists of descriptors.

Abstract: A method and system for capacitor based digital to analog converter design layout for high speed analog to digital converter are provided. The method includes arranging a plurality of metal plates to form the capacitor. Each of the plurality of metal plates includes a driven plate and a common plate. The method also includes generating a plurality of interconnects in the common plate and extending the driven plate over the plurality of interconnects. Further, the method includes shielding the common plate by the driven plate. The system includes an analog to digital converter. The analog to digital converter also includes capacitor based digital to analog converter and digital logic for controlling digital operations in the analog to digital converter. The capacitor based digital to analog converter includes a plurality of capacitors, and a comparator for comparing the analog output from the digital to analog converter with a ground potential.

Abstract: Evaluation of Multiple XPath Queries in a Streaming XPath Processor. A hit of a location path is determined in a SAX event. All XPath queries corresponding to the location path are then identified. XML nodes associated with the SAX event is identified as potential output nodes for all XPath queries including the location path as a main location path. The potential output nodes are nodes satisfying criteria of a node test of a last location step of the main location path. The potential output nodes are then buffered for all XPath queries comprising unevaluated predicates. For each XPath query the potential output nodes are buffered at a location step including an unevaluated predicate. Thereafter, all XPath queries are evaluated by progressively evaluating the unevaluated predicates of all XPath queries based on availability of data.

Abstract: A method for biasing a MOS transistor includes AC coupling an input signal from an amplifier stage to a gate of the MOS transistor. The method includes connecting a pair of diodes in an opposing parallel configuration to a bias transistor and a current source. Further, the method includes generating a DC bias voltage through the bias transistor and the current source. The method also includes clamping the voltage at drain of the bias transistor to a fixed voltage by a clamping circuit. Further, the method includes coupling the DC bias voltage to the gate of the MOS transistor through the pair of diodes.

Abstract: Modifying Xpath queries dynamically during an ongoing Xpath evaluation. A modification request comprising at least one Xpath query in response to an input is received in an ongoing Xpath evaluation on an online stream of XML messages. A current generation of Nondeterministic Finite Automaton (NFA) is generated and the branches starting from the root node are identified according to the modification request. The identified branches are copied and modified to create a new generation of NFA. New generation of NFA is used for subsequent Xpath evaluations.

Abstract: Simplified XPath evaluation in Extensible Markup Language (XML) document validation. XML schema is compiled into a one dimensional array of schema nodes, where a schema node represents a complex/simple type definition in the XML scheme. Identity constraints are processed during compilation and Xpath expressions within these constraints are extracted and parsed. Further, these Xpath expressions are evaluated at compilation time to identify the schema nodes corresponding to the XML nodes referred in the identity constraints. The identity constraints are then enforced at runtime without the need to evaluate the Xpath expressions at the runtime.

Abstract: Single inductor multiple output (SIMO) switching devices with efficient regulating circuits. The SIMO switching device includes a plurality of time division multiplexing (TDM) switches for switching current through an inductor of the SIMO switching device. The plurality of TDM switches produces a plurality of outputs. The SIMO switching device further includes an error calculation circuit operatively coupled to the plurality of outputs for determining a calculated error from the plurality of outputs; a time slot generation circuit for controlling the plurality of TDM switches according to the calculated error; and a pulse width modulation (PWM) control circuit operatively coupled to the time slot generation circuit for controlling a plurality of PWM switches of a switching stage of the SIMO switching device in a continuous conduction mode (CCM) of operation. The PWM switches are controlled according to the time slots generated by the time slot generation circuit.

Abstract: A Read only memory (ROM) with minimum leakage includes a ROM array including a first transistor, wherein a drain, a source, a gate, and a bulk of the first transistor is electrically connected to a logic zero in the idle state for ensuring zero junction and sub-threshold leakage current. The drain of the first transistor is electrically connected to a main bit line through a second transistor. The second transistor includes a gate, electrically connected to a first decoding circuit, a drain, electrically connected to the main bit line. A first reference bit line is electrically connected to a drain of a third transistor, wherein gate of the third transistor is electrically connected to a second decoding circuit for generating a stop read signal. A second reference bit line, electrically connected to the first decoding circuit through a first sensing unit for generating a stop pre-charge signal.

Abstract: Read only memory (ROM) with minimum leakage is provided. The ROM includes a read only memory array. The read only memory array includes a first transistor, wherein a drain, a source, a gate, and a bulk of the first transistor is electrically connected to a logic zero in the idle state for ensuring zero junction and sub-threshold leakage current. Another ROM includes a first transistor comprising a gate, electrically connected to a word line to provide a read signal, a drain, electrically connected to a main bit line through a second transistor. The second transistor includes a gate, electrically connected to a first decoding circuit, a drain, electrically connected to the main bit line. A first reference bit line is electrically connected to a drain of a third transistor, wherein gate of the third transistor is electrically connected to a second decoding circuit for generating a stop read signal.

Abstract: Power supply regulation. A power supply regulation system includes a transistor through which power is carried. The system also includes a switch connected to a gate of the transistor. Further, the system includes a transmission gate responsive to an input signal to apply a first signal level causing the transistor to enter an ON state in which the transistor carries full power, to apply a second signal level causing the transistor to enter an OFF state in which the transistor carries no power and to apply a third signal level causing the transistor to enter an INTERMEDIATE state in which the amount of power the transistor carries is controlled by the switch.

Abstract: Classifying Uniform Resource Identifier (URI) expression using one or more XPath expressions. A request comprising a URI expression and additional network information is modeled as a logical XML document representation. One or more XPath expressions are then created from the schema of the logical XML document. Each of the one or more XPath expressions represents a classification category of the request. Further, an XML document is generated from an incoming request. One or more XPath expressions are evaluated on the XML document for classifying the incoming request.

Abstract: A computer is programmed to prepare a computer program for simulating operation of an integrated circuit (IC) chip, in order to test scan circuitry therein. The computer is programmed to trace a path through combinational logic in a design of the IC chip, starting from an output port of a first scan cell and ending in an input port of a second scan cell. If the first and second scan cells receive a common scan enable signal, then the computer generates at least a portion of the computer program, i.e. software to perform simulation of propagating a signal through the path conditionally, for example when the common scan enable signal is inactive and alternatively to skip performing simulation when the common scan enable signal is active. The computer stores the portion of the computer program in memory, for use with other such portions of the computer program.

Abstract: An efficient implementation of a digital delay locked loop (DLL) circuit is disclosed. The delay locked loop (DLL) circuit includes a phase detector circuit, a clock divider circuit, a delay, a delay control finite state machine (FSM) and an output low pass filter. The delay includes a coarse delay line and a fine delay line. The coarse delay line delays a signal by a fixed large amount and the fine delay line introduces a smaller precise delay. The delay control FSM adjusts the delay to keep the output signal of the DLL synchronized with the input. The adjustment is averaged over a range of cycle periods in order to avoid adjusting the edges of signal waveform constantly. The low pass filter at the output minimizes the jitter in the output signal.

Abstract: Improving statistical yield of a system-on-a-chip. The system-on-a-chip includes several memory systems. Each memory system includes a large number of memories. The memories are tested to identify any faulty memories. One or more margins of the faulty memories are then varied and the memories are then tested again.