Abstract: The invention provides a method and apparatus for the prevention of fraudulent toll calls by a user connected to a key telephone system. On recognition of a user request for use of a telephone line to make a call to a destination outside the key system, the forward speech path to the seized telephone line is muted. The string of digits dialed by the user are monitored and evaluated for correspondence to restrictions associated with the user terminal. If restrictions are failed, the call is terminated; otherwise, the forward speech path is unmuted and the call is allowed to proceed in the conventional manner. The invention may also provide an interdigital timer which is set upon reception of each dialed digit whereby if the timer is allowed to reset while the dialed digit string is being monitored, the call is terminated.

Abstract: A circuit for providing a phase controlled clock output includes a ring oscillator having a delay line for providing an internal clock signal whose period varies with on-chip variations due to temperature, voltage, and process. The circuit also includes a clock phase select circuit having a counter and divider for determining the number of delays in one external clock period and an input for a phase select value. A delay line having delay elements similar to those of the ring oscillator provides multiple delayed clock signals from the reference clock signal. A multiplexor having odd and even sides is used to select the desired clock signal in a glitchless manner. The phase controlled clock signal output is controlled by the phase select signal and is compensated for on-chip variations due to temperature, voltage, and process.

Abstract: A voice bus on a computer backplane provides point-to-point connection between a plurality of slots on the backplane to a particular slot. Connection from the plurality of slots is provided by third connectors which lie between first and second connectors defining the slots. Connection to the particular slot is via its respective second connector. In particular, the computer backplane is physically and electrically compatible with the IEEE standard 1014-1987 defining the VMEbus. The presence of the third connector is compatible with the VMEbus standard both electrically and physically.

Abstract: A digital phase-locked loop circuit includes circuitry for generating substantially periodic recovered clock signals each one corresponding to a discrete amount of delay from a local clock signal. Incremental delay is added or subtracted at each clock generation cycle until the data input signal and the last-generated recovered clock signal are substantially phase-aligned. The circuit includes delay measurement circuitry for dynamically measuring the smallest quantity of delay units required to provide at least a 360 degree phase shift of the local clock signal. The circuitry for generating the recovered clock signals is then constrained to generate clock signals having a maximum delay corresponding to the last-measured quantity of delay.

Abstract: A VME Bus Compatible backplane and shelf arrangement is provided which incorporates a connectorized backplane arrangement which provides for direct mating to both industry standard VME bus cards as well as VME transition cards. A backplane is provided that is double-sided. On a first face, access to two VME busses (P1 & P2) is provided via rows of first and second connectors. The connector of each row are evenly spaced along the bus and the connectors of one row are vertically aligned with the connectors of the second row. On the second face a third row of connectors is provided, directly behind the second row with each connector offset with respect to a corresponding second connector. The first and second rows of connectors accept standard VME bus cards. The third connectors accept directly, industry standard transition cards. Some of the conductors in the second connectors are connected to the second bus, while others are connected directly to conductors in the third connectors.

Abstract: A method and circuit utilizing first and second tag bits for granting access to a block of memory in a multiprocessor system having a shared memory are provided. When a memory request for exclusive access to a block of memory is granted, the starting address for that block of memory is placed in a register bank, thereby opening a semaphore. The starting address of a memory block of a subsequent memory access request is compared with the starting addresses corresponding to open semaphores within the register bank and access is denied to the requested block of memory if a match is found. The starting address associated with a request which is denied access is placed in a temporary buffer and the request is later granted access after the corresponding open semaphore becomes closed. A request which is granted memory access to a memory block which results in an open semaphore, has exclusive access to that block of memory until the semaphore is closed.

Abstract: A method and circuit for prefetching is provided wherein selective caching of instructions occurs. An instruction execution tree comprising a plurality of instructions is traversed in a predetermined manner. Instructions depending from both paths of a conditional branch instruction are prefetched. When it is determined that a branch of prefetched instructions is not in the path of execution the instructions associated with that branch are deleted thereby pruning the branch. Instruction addresses are therefore selectively removed from a storage memory in such a manner as to provide the cache with instructions which will likely be required by the processor.

Abstract: A cache memory functioning as a circular buffer for use as a part historical, part predictive cache memory is provided. A first register contains data having a value corresponding to a cache memory location of a last instruction executed by a processor and a second register contains data having a value corresponding to a memory location in the cache memory of a last prefetched instruction. Prefetching of instructions from a main memory to the cache memory is disabled if the difference between the values in the first and second pointer registers exceeds a predetermined amount.

Abstract: A circuit for testing the integrity of transmission paths includes a first linear feedback shift register (LFSR) adapted to generate a periodic sequence of pseudo random test data for transmission on the transmission paths. A second LFSR synchronizes to the transmitted test data after being provided with a seed value corresponding to a transmitted data word. After synchronization, the second LFSR is set to a free running mode and independently generates a pseudo random sequence of patterns corresponding to the sequence generated by the first LFSR. A comparator compares the pseudo random data generated by the second LFSR with the pseudo random data received from the transmission paths. If a mismatch occurs a signal indicating an error condition is asserted.

Abstract: The invention provides a pseudo set-associative memory cacheing arrangement for use in a data processing system comprising a processor interfacing to a main memory and adapted to support a cache memory. The arrangement comprises a plurality of cache memory banks each comprising a respective number of addressable locations individually defined by a cache address. A plurality of cache select circuits are each associated with a respective one of the cache memory banks and each one is responsive to m most significant bits of a main memory address and control signals for mapping its associated cache memory bank to a predetermined range of addresses in main memory.

Abstract: The invention provides a duplex processor arrangement wherein the processors are only pseudo-synchronized to each other. Each processor is provided with its own independent clock circuit and the two clock circuits operate at the same nominal frequency. A circuit means is provided for periodically forcing a rendezvous between processors whereat a controller circuit ensures that the processors have processed the same information since the last rendezvous. Each processor comprises a match circuit including memory means connected to store address/data information related to instructions performed by the processors. Each match circuit compares the information from the processors and generates an alarm signal upon a mismatch.

Abstract: A simulation model is provided which comprises a combination of software models and a hardware model. Induced off-circuit behavior of the hardware model during simulation is achieved by presenting it with off-circuit input patterns and sampling the resulting output patterns. After sampling, the hardware model is reset to its state prior to the presentation of the off-circuit patterns thereby causing the simulation to resume and preserving the integrity of the simulation.

Abstract: The reliability of conductive circuitry of a printed circuit board and particularly the integrity of the conductive barrels of the through-holes is tested by cyclically passing a current through a plurality of interconnected barrels. The current must be sufficient to resistively heat the conductive barrels to a temperature at which the glass epoxy substrate adjacent to each barrel reaches a transition temperature at which the glass epoxy changes state from a solid to a semi-solid. After sufficiently heating the glass epoxy, it is allowed to cool to ambient temperature. This cycle is repeated for a predetermined number of cycles and the resistance of the barrels is measured after each cycle. A measured resistance that exceeds a predetermined value indicates that one or more defects is present in the interconnected barrels.

Abstract: An active intelligent termination circuit is designed to function as a self-switching clamp adapted to attenuate unwanted signals on a data bus. A field effect transistor is switched on or off in a conducting mode or non-conducting mode respectively in accordance with the data transmitted on the data bus. Any low level unwanted signals which may appear on the bus when data having a voltage level corresponding to a logic zero is present will be attenuated by the field effect transistor which is coupled to both the data bus and to a ground plane. The field effect transistor switches to the non-conducting mode when data corresponding to a logic level one is transmitted on the bus.

Abstract: A ground integrity monitor for testing for a short circuit between two equipotential ground planes having a single common connection point includes an AC generating circuit for coupling to one of the ground planes a signal having predetermined frequency and magnitude characteristics. An AC detecting circuit coupled to the other of the ground planes is adapted to detect the AC signal within a predetermined range of magnitude and frequency. Presence of the signal on the other ground plane indicates the existence of a short circuit.

Abstract: Signaling bits (ABCD) from a plurality of channels are coded in a predetermined manner, multiplexed into a serial bit stream and transmitted on a data path. A receiver for the data includes a multiple level state machine adapted to decode and synchronize to the received coded signaling bits. Each level of the state machine is associated with a perspective type of signaling bit and the levels of the state machine are cascaded output to input. The existence of an output signal from the last stage of the state machine indicates the receiver is synchronized to the serial bit stream and thus the receiver is properly decoding and identifying the signaling bits.

Abstract: The invention provides a digital clock circuit for providing an output clock signal having a frequency varying between predetermined limits. A digital frequency changer circuit is responsive to a fixed frequency signal and to control signals for generating the output clock signal. A circuit means is responsive to a variable reference signal and to the output signal of the clock circuit for generating a binary control word representative of a frequency difference therebetween. A rate multiplier circuit is responsive to the binary control word and the output clock signal for generating the control signals. The only non-digital component of the clock circuit is a local crystal oscillator.

Abstract: A data receiver interface circuit is provided with a circuit for accepting correctly framed data. The plurality of data bits sandwiched between a pair of frame pulses is temporarily stored while the number of clock cycles occurring between the frame pulses is determined to be a valid number. The data is accepted by the receiver if the number of clock cycles occurring between the pair of successive frame pulses is a valid number.

Abstract: A phase locked loop has a phase detector which receives an input signal, a divided output signal from a VCO and a local clock signal, and produces a binary number representing the phase relationship between the input and divided signals. The binary number is applied to a microprocessor which compares it to a predetermined number n and controls the VCO through a D/A converter. To reduce output signal jitter, the microprocessor adjusts the VCO frequency so that the binary number alternates between n and n--1 or between n and n+1.

Abstract: The invention provides a telecommunications system exhibiting an architecture having a plurality of functional levels decoupled from one another by data transport systems. The communication facilities connected to the periphery of the system are terminated at the physical level only and the data is channelized for transmission through a channel switch to a first level of processing that provides channel services. The data is then multiplexed and transmitted to system and call processing resources via a frame transport system.