Abstract: A CMOS shift register cell comprising four transistors and two capacitance elements. Data is temporarily stored in the cell by precharging one capacitance through one of the transistors and then discharging it or not through another of the transistors depending on the input signal level. The second capacitance may be precharged through the third transistor and then discharged or not through the fourth transistor, depending upon the value of the temporarily stored charge.

Abstract: In the "on" condition of the circuit, a current mirror supplies a bias current to a comparator, a voltage divider circuit supplies a reference voltage to one input terminal of the comparator, and the input voltage to be compared to the reference voltage is applied to the other input terminal of the comparator. In the "off" condition of the circuit, the current mirror, the comparator and the voltage divider circuit are all cut off to reduce to substantially zero the power consumption of the circuit. The comparator employs regenerative feedback to increase switching speed and gain and minimize the offset voltage. The bias current amplitude is automatically adjusted in response to reference voltage changes, thereby maintaining the bias current level at the value desired for a particular reference voltage.

Abstract: An oscillator utilizing a voltage comparator having hysteresis characteristics for producing a pulse train. The width of the pulses in the train is controlled by the charging rate of a capacitor coupled to one input of the comparator and the period of the pulse train is controlled by the discharge rate of this capacitor. The discharge rate and hence the oscillator frequency may be varied in response to a control voltage. Compensating elements ensure that the pulse width is highly stable with respect to temperature variations. The oscillator when in a feedback control circuit, produces oscillations at a frequency whose value is linearly related to the feedback control voltage.

Abstract: The circuit comprises three current mirrors, the first and second having at least two output current paths and the third, one output current path. The first mirror is complementary to the second and supplies its output currents to the second. The signal current is applied to the second mirror and affects the output currents of the second mirror. The third mirror has an input circuit which serves as a shunt path for one of the output currents supplied by the first mirror in excess of that which the second mirror can accept and an output circuit which, under the same conditions, receives a portion of the second output current supplied by the first mirror. The load, through which flows a current which has the absolute value of the signal current, is coupled to the output terminal of the third mirror.

Abstract: An automated test set for determining the reverse biased second breakdown characteristics of a bipolar transistor without destroying or degrading the transistor under test (TUT). A source supplies current to the TUT through an inductor. The amplitude of this current increases in predetermined increments. After each current amplitude increase, the base-emitter junction of the TUT is reverse biased and the source is disabled. If enough energy is stored by the inductor to cause second breakdown, this breakdown is detected and the test is terminated. Otherwise, the test continues until the test current reaches a predetermined maximum amplitude, at which time the test is terminated. Damage to the TUT is avoided by restricting the stored energy to levels high enough to cause second breakdown but low enough that the remaining energy does not cause thermal damage.

Abstract: A semiconductor memory cell whose supply voltage is decoupled from the cell voltage bus during a write operation. Automatic return of the bus to the supply voltage level once the static state is reached, even though a write command is still present, is achieved by supplying operating voltage to the cell bus from one of the data lines via a conducting transistor.

Abstract: A circuit for generating a logic function and its logical complement of N binary variables utilizing MOS transistors which are all of the same conductivity type. The circuit may include an N input NAND gate comprising N MOS transistors and a load element, the conduction paths of the transistors connected in series with the load element to form a first series circuit and an inverter circuit having N+1 MOS transistors, the conduction paths of which are connected in series to form a second series circuit. Each series circuit is connected between the same operating voltage terminals and the two are interconnected to one another in such manner that the power dissipation of the circuit compares favorably with a CMOS inverter.