Abstract: A system and method for controlling performance and/or power based on monitored performance characteristics. Various aspects of the present invention may comprise an integrated circuit comprising a first circuit module that receives electrical power. A second circuit module may monitor one or more performance characteristics of the first circuit module and/or the integrated circuit. A third circuit module may, for example, determine power control information based at least in part on the monitored performance characteristic(s). The power control information may be communicated to power supply circuitry to control various characteristics of the electrical power. Various aspects of the present invention may also comprise an integrated circuit comprising a first module that monitors at least one performance characteristic of a first electrical device.

Abstract: There is provided a system and method for an ontological and rules based segmentation engine for networked content delivery. There is provided a segmentation engine for use by a network accessible computing device providing customized content for a user on the network, comprising a user context regarding the user, a content management system for storing content, a controlled vocabulary categorizing content, an ontology using the controlled vocabulary for referencing the content of the content management system, segment definitions grouping users into segments matching content types to controlled vocabulary elements, segment rules using user context to associate with segment definitions, and a segmentation processor. The segmentation processor can receive a content request from the user, and by using the elements of the segmentation engine, determine the segment definitions applicable to the user and provide customized content from the content management system.

Abstract: According to one exemplary embodiment, a method for determining a self-heating free drain current in a transistor corresponding to a channel temperature not affected by a drain DC current includes measuring at least three unique drain currents of a transistor corresponding to at least three unique ambient temperatures. The method further includes determining at least three unique channel temperatures of the transistor corresponding to the at least three unique drain currents, thereby establishing a current-temperature relationship for the transistor. The method further includes determining the self-heating free drain current of the transistor utilizing the current-temperature relationship.

Abstract: A trench type power semiconductor device which includes deposited rather than grown oxide in the trenches for the electrical isolation of electrodes disposed inside the trenches from the semiconductor body.

Abstract: According to one exemplary embodiment, a method for monitoring structural integrity of at least one fuse in semiconductor wafer, which includes at least one electrical monitoring structure, includes forming a monitoring window in a dielectric layer overlying the at least one electrical monitoring structure, where the monitoring window and a fuse window overlying the at least one fuse are, in one embodiment, formed in a same etch process. The method further includes performing at least one electrical measurement on the at least one electrical monitoring structure, wherein the at least one electrical measurement is utilized to monitor the structural integrity of the at least one fuse. A change in the at least one electrical measurement is utilized to indicate a change in the structural integrity of the at least one fuse. The at least one electrical monitoring structure can include, for example, a metal serpentine line and one or more metal combs.

Abstract: Aspects of a method and system for an integrated antenna and antenna management are provided. In this regard, one or more reactances coupled to an antenna in a hybrid circuit may be tuned and signals may be transmitted and/or received based on the tuning. The hybrid circuit may comprise an integrated circuit (IC) bonded to a multi-layer package. The antenna may be embedded within and/or on the multi-layer package. The reactances may be within and/or on the IC and/or the multi-layer package. In this regard, the IC may be bonded to or mounted to an underside of the multi-layer package. The reactances may be tuned via one or more switching elements and/or logic, circuitry, and/or code within the IC. The reactances may comprise one or more inductors and/or capacitor arrays. The multi-layer package may comprise one or more layers of ferromagnetic and/or ferrimagnetic material.

Abstract: A method of enabling identification of information content having enhanced desirability to a user comprises collecting content into an information database, updating the collected content according to one or more updating schedules, filtering the updated content by reference to at least one theme, associating each of the filtered content items with a respective visual representation, and labeling the respective visual representations with one or more visual cues corresponding to one or more discrimination criteria. A system for enabling same comprises an information database configured to store collected content and accessible via a content server, an aggregator configured to update the collected content, an interactive content selection application configured to provide a user interface enabling filtering of the updated collected content, and a visualization module configured to associate the filtered content items with a visual representation and label each with one or more visual cues.

Abstract: A lateral DMOS transistor that includes two RESURF regions of one conductivity and two RESURF regions of another conductivity disposed between the base region and the drain region thereof.

Abstract: A power semiconductor device that includes a trench power MOSFET with deep source field electrodes and an integrated Schottky diode.

Abstract: There is provided a method of enabling client-side initiated delivery of dynamic secondary content to a host page comprising running a dynamic secondary content delivery application, requesting a secondary content update to one or more items of existing secondary content rendered on the host page during page load, downloading the secondary content update to the client system, parsing the secondary content update by the dynamic secondary content delivery application, and rendering the secondary content update on the host page, resulting in the client-side initiated delivery of the dynamic secondary content to the host page. In one embodiment, the method is executed by a client system in response to instructions comprising the dynamic secondary content delivery application stored on a computer-readable medium.

Abstract: An integral impedence is formed on or within a lead frame pin of a semiconductor package and receives a connection from an electrode of a semiconductor die within the package to eliminate the need for adjustment and protective impedences external of the package. The impedence comprises passives such as resistors, capacitors, diodes or inductors which modify the performance of the package for new semiconductor device characteristics. The impedences may have positive or negative temperature coefficients and are in close thermal communication with the semiconductor die.

Abstract: An integrated circuit with a semiconductor substrate is provided. A gate dielectric is on the semiconductor substrate, and a gate is on the gate dielectric. A metallic layer is on the semiconductor substrate, and the metallic layer is reacted with the semiconductor substrate to form an early phase of silicide. Implanted shallow source/drain junctions are immediately beneath the silicide. A final phase of the silicide is formed. An interlayer dielectric is above the semiconductor substrate, and contacts are formed to the silicide.

Abstract: According to one exemplary embodiment, a p-channel germanium on insulator (GOI) one transistor memory cell comprises a buried oxide (BOX) layer formed over a bulk substrate, and a gate formed over a gate dielectric layer situated over a germanium layer formed over the buried oxide (BOX) layer. A source region is formed in the germanium layer adjacent to a channel region underlying the gate and overlaying the BOX layer, and a drain region is formed in the germanium layer adjacent to the channel region. The source region and the drain region are implanted with a p-type dopant. In one embodiment, a p-channel GOI one transistor memory cell is implemented as a capacitorless dynamic random access memory (DRAM) cell. In one embodiment, a plurality of p-channel GOI one transistor memory cells are included in a memory array.

Abstract: A gate driver for performing gate shaping on a first transistor of having gate, source, and drain terminals, the first transistor being selected from a switching stage of a power switching circuit having high- and low-side transistors series connected at a switching node for driving a load. The gate driver includes the following steps: upon receipt of an ON pulse pre-charging the gate terminal until gate to source terminal voltage equals Vth, controlling the di/dt(ON) flowing in the first transistor while free wheeling current is flowing in a second transistor of the switching stage, and controlling the dv/dt(ON) of the first transistor while a charge on the gate terminal is present; and upon receipt of an OFF pulse controlling the dv/dt(OFF) of the first transistor until free wheeling current is flowing in the second transistor, and controlling the di/dt(OFF) flowing in the first transistor while the gate to source terminal voltage equals Vth.

Abstract: According to an exemplary embodiment, a liquid crystal on silicon (LCoS) structure includes a number of pixel electrodes overlying an interlayer dielectric, where diagonally adjacent pixel electrodes are separated by a gap. The LCoS structure further includes a self-planarizing passivation dielectric situated over the pixel electrodes and in the gap, where the self-planarizing passivation dielectric has a selected thickness. The self-planarizing passivation dielectric can be an Oxide-Nitride-Oxide (ONO) stack. The selected thickness of the self-planarizing passivation dielectric causes the self-planarizing passivation dielectric to have a substantially planar top surface. In one embodiment, the thickness of the self-planarizing passivation dielectric can be approximately equal to twice a width of the gap.

Abstract: A method for manufacturing a semiconductor package that includes forming a frame inside a conductive can, the frame being unwettable by liquid solder.

Abstract: According to one exemplary embodiment, a differential varactor circuit for a voltage controlled oscillator having two differential outputs includes a first varactor having first and second terminals and a second varactor having first and second terminals. In the differential varactor circuit, each of the first and second terminals of the first varactor and each of the first and second terminals of the second varactor are coupled to one of the two differential outputs of the voltage controlled oscillator, thereby allowing a size of each of the first and second varactors to be reduced so as to increase varactor quality factor. Each of the first and second terminals of the first varactor can be coupled to one of the two differential outputs by a capacitor, and each of the first and second terminals of the second varactor can be coupled to one of the two differential outputs by a capacitor.

Abstract: Certain aspects of a method and system for an antenna architecture for multi-antenna orthogonal frequency division (OFD) based systems are disclosed. Aspects of one method may include communicating data in a radio frequency (RF) system comprising a plurality of antennas, via at least one polarized antenna that is orthogonally polarized with respect to adjacent polarized antennas. The plurality of coherently polarized antennas may be placed at a particular distance from each other.

Abstract: In one embodiment a method enabling in situ dopant implantation during growth of a III-nitride semiconductor body, comprises establishing a growth environment for the III-nitride semiconductor body in a composite III-nitride chamber having a dopant implanter and a growth chamber, growing the III-nitride semiconductor body in the growth chamber, and implanting the III-nitride semiconductor body in situ in the growth chamber using the dopant implanter. A semiconductor device produced using the disclosed method comprises a III-nitride semiconductor body having a first conductivity type formed over a support substrate, and at least one doped region produced by in situ dopant implantation of the III-nitride semiconductor body during its growth, that at least one doped region having a second conductivity type.

Abstract: Some exemplary embodiments of an advanced direct contact leadless package and related structure and method, especially suitable for packaging high current semiconductor devices, have been disclosed. One exemplary structure comprises a mold compound enclosing a first contact lead frame portion, a paddle portion, and an extended contact lead frame portion held together by a mold compound. A first semiconductor device is attached on top of the lead frame portions as a flip chip, while a second semiconductor device is attached to a bottom side of said paddle portion and is in electrical contact with said the first semiconductor device. The extended contact lead frame portion is in direct electrical contact with the second semiconductor device without using a bond wire. Alternative exemplary embodiments may include additional extended lead frame portions, paddle portions, and semiconductor devices in various configurations.