Abstract: A CAM cell comprises a pair of SRAM cells, each of which comprise a pair of cross coupled inverters for storing a data value and a pair of access devices for accessing a complementary pair of bit lines. The CAM cell further comprises a pair of compare circuits, each for comparing said data value stored in one of said SRAM cells with a search data value provided on a corresponding search line. The CAM cell has an equivalent number of n-channel and p-channel devices. The CAM cell uses p-channel transistors as access transistors to the SRAM cells in order to improve the efficiency of the layout of the cell array. The implementation ensures a balanced number of p-channel and n-channel devices per cell while still providing excellent functional characteristics.

Abstract: This invention describes an improved high bandwidth chip-to-chip interface for memory devices, which is capable of operating at higher speeds, while maintaining error free data transmission, consuming lower power, and supporting more load. Accordingly, the invention provides a memory subsystem comprising at least two semiconductor devices; a main bus containing a plurality of bus lines for carrying substantially all data and command information needed by the devices, the semiconductor devices including at least one memory device connected in parallel to the bus; the bus lines including respective row command lines and column command lines; a clock generator for coupling to a clock line, the devices including clock inputs for coupling to the clock line; and the devices including programmable delay elements coupled to the clock inputs to delay the clock edges for setting an input data sampling time of the memory device.

Abstract: A system and method for use in a real time system and for processing a signal with a low signal-to-noise ratio (SNR). The system comprises a model for modeling an expected signal and a filter that uses the model for filtering the signal. The filter is used for generating a prediction of the signal and an error variance matrix. The system further comprises an adaptive element for modifying the error variance matrix such that the bandwidth of the filter is widened, wherein the filter behaves like an adaptive filter.

Abstract: A frequency multiplier circuit comprising a delay line receiving at one end thereof a reference clock for generating clock tap outputs from respective ones of a plurality of period matched delay elements; a clock combining circuit responsive to pairs of tap outputs for generating a rising and falling edge of an output clock pulse from respective ones of the pairs whereby the output clock period is less than the input clock period.

Abstract: A method for performing a sense and restore operation in a multilevel DRAM is described. The method describes the selective enabling of the sense amplifiers to operate at predetermined sensing thresholds. The multilevel DRAM stores two bits per cell using a four-voltage-level-per-cell system. Folded bitlines are divided into sub-bitlines each having dedicated sense amplifiers. The sense amplifiers are selectively enabled to operate at predetermined sensing thresholds to thereby greatly simplify the sense and restore operations. The circuit has standard CMOS bitline sense amplifier transistors connected thereto with pull down transistors that may be selectively enabled by switch signals. The length and width of these pull down transistors are varied to thereby effect the switching threshold of the sense amplifier.

Abstract: A method for performing a sense and restore operation in a multilevel DRAM is described. The method describes the selective enabling of the sense amplifiers to operate at predetermined sensing thresholds. The multilevel DRAM stores two bits per cell using a four-voltage-level-per-cell system. Folded bitlines are divided into sub-bitlines each having dedicated sense amplifiers. The sense amplifiers are selectively enabled to operate at predetermined sensing thresholds to thereby greatly simplify the sense and restore operations. The circuit has standard CMOS bitline sense amplifier transistors connected thereto with pull down transistors that may be selectively enabled by switch signals. The length and width of these pull down transistors are varied to thereby effect the switching threshold of the sense amplifier.

Abstract: Cryptographic methods are disclosed, which allow a prover party, who holds a number of secrets, to demonstrate satisfiable formulas of propositional logic, wherein the atomic propositions are linear relations between the secrets. The demonstration reveals no more information than is contained in the formula itself. Some implementations allow an unlimited number of such demonstrations to be made, without revealing any additional information about the secrets, whereas other implementations ensure that the secrets, or some of the secrets, will be revealed, if a demonstration is performed more than a predetermined number of times. The demonstrations may be zero-knowledge proofs, or signed proofs.

Abstract: An automated vehicle tracking and service provision system including a central controller, a local controller located in each vehicle, the central controller and the local controllers including wireless communication interface for communication of information between the central controller and the vehicle based on fuzzy logic algorithms decision making software.

Abstract: The present invention relates to a system for providing a communication network, comprising: an intranet-connected server having input and access capabilities; a means on the server for receiving instructions input from a first user and for creating a dedicated intranet site based on the received instructions; means to communicate existence of the dedicated intranet site to a nominated second user; means to access contents of the dedicated intranet site by the second user via a web-browser installed on the second user; and means to store information in the dedicated intranet site input via a web-browser installed at the first or the second user.

Abstract: A semiconductor device having a self test circuit including an embedded dynamic random access memory array for storing data, a self test controller for internally generating test data patterns and expected resulting data and for comparing the expected resulting data with actual resulting data, test interface circuitry for loading the test data patterns into the memory and reading back the actual resulting data from the memory, means for selectively programming a voltage level to be applied to a selected cell plate of the memory according to predetermined test requirements and means for storing an address of a defective memory cell. In addition, the semiconductor device includes means for repairing a defective memory row or column in response to a signal received from the self test controller.