Abstract: Provided are a method and system for achieving enhanced performance in communications between a plurality of emulated networks overlaid onto at least one base network, wherein the communications involve one or more source route bridges. The method and system accomplish their objects via the following. Determining when communication is to occur, through the one or more source route bridges, and between at least two entities where a first of the at least two entities is a member of a first emulated network and where a second of the at least two entities is a member of another of the plurality of emulated networks. Informing the at least one of the at least two entities of one or more addresses consonant with the protocols of the at least one base network wherein the one or more addresses identify one or more base network entities closely correspondent to at least one of the at least two entities.

Abstract: A cache and method of maintaining cache coherency in a data processing system are described. The data processing system includes a plurality of processors that are each associated with a respective one of a plurality of caches. According to the method, a first data item is stored in a first of the caches in association with an address tag indicating an address of the data item. A coherency indicator in the first cache is set to a first state that indicates that the data item is valid. In response to another of the caches indicating an intent to store to the address indicated by the address tag while the coherency indicator is set to the first state, the coherency indicator in the first cache is updated to a second state that indicates that the address tag is valid and that the first data item in the first cache is invalid.

Abstract: A method of handling a cache error (such as a parity error), which allows a software recovery, by reporting the error using an unrelated system resource, such as an interrupt service, and particularly a data storage interrupt. The parity error can be reported by generating a data storage interrupt and using the data storage interrupt status register (DSISR) to indicate that the data storage interrupt is a result of the parity error. The context of the processor can be fully synchronized while handling the parity error.

Abstract: A process for producing a substantially dry polymer particle powder. A mixture of polymerization reagents is formed from a mixture of at least one monomer source and a solvent selected from the group consisting essentially of water and organic solvents and an initiator source. The mixture of polymerization reagents is sprayed into a heated, controlled atmosphere, forming droplets of the mixture which are allowed to fall through the heated, controlled atmosphere for a sufficient period of time to obtain a desired degree of polymerization. The solvent is continuously evacuated from the atmosphere during the polymerization process.

Abstract: A method and apparatus for testing a modem line in a data processing system, wherein the data processing system includes a modem having an input for a modem line. The input is tested to determine an electrical connection network is present.

Abstract: A method and apparatus for testing a modem line in a data processing system, wherein the data processing system includes a modem having an input for a modem line. The input is tested to determine an electrical connection network is present.

Abstract: A method and system in an information processing system are disclosed for efficiently maintaining copies of values stored within a plurality of registers. The information processing system includes first circuitry, second circuitry, and a plurality of buffers. The first circuitry processes an execution state of a first type of instruction which always specifies a destination of at least one of a first type of register or a second type of register, and which outputs first information in response thereto. The first circuitry also processes an execution stage of a second type of instruction which always specifies a destination of only a third type of register, and outputs second information in response thereto.

Abstract: A method of providing a value to a cache used in a computer system, by transmitting the value from a system memory device to a lower level (e.g., L2) of the cache using a system bus, acknowledging the forwarding of the address from the lower level of the cache after said transmitting of the value, and acknowledging the forwarding of the address from a higher level (e.g., on-board) of the cache, in response to said transmitting step. The acknowledging of the forwarding of the address from the higher level of the cache, can occur prior to the acknowledgment of the forwarding of the address from the lower level of the cache. The value is transmitted from the lower level of the cache to the higher level of the cache using the higher level bus, in response to said acknowledgement of the forwarding of the address from the higher level of the cache, and this latter transmission can also occur prior to said acknowledgment of the forwarding of the address from the lower level of the cache.

Abstract: A shower enclosure system includes an elongate arcuate rod having first and second spaced end portions, a pair of swivels, with one swivel at each of the end portions, and a pair of swivel-receiving wall mounts for mounting on opposing walls of a shower enclosure, with each of the swivels to receive one of the swivels. The system includes a shower curtain rod which is shaped so that the bathroom is protected by draping the shower curtain in such a way that splashed water does not escape from the bath tub. The shape of the curtain rod provides added space outside the perimeter of the tub footprint, for the comfort of the user within the shower enclosure. However, the added space within the shower enclosure does not compromise the integrity of the water capturing function of the shower curtain.

Abstract: A travel guide device includes a GPS receiver for determining a present location. Access to a database of points-of-interest, indexed by GPS location, is provided to permit timely presentation of audio narration or visual display of information relevant to the point-of-interest. A running, general area narrative and/or display may alternatively be provided. The travel guide device may provide educational and entertaining games, including interactive competitive games, relating to the points-of-interest and general area narratives. A navigation function includes automatic, intelligent collection of waypoints and general directions without stored, detailed maps of an area for which directions are being provided. Waypoint collections may be employed to document a route travel, to retrace the route, or for other purposes.

Abstract: The current invention is a universal anchor for use with both ring clutches and bail lift clutches. The invention includes an anchor with a nail-shaped head on one end of a shaft and a flattened plate with at least one perforation through the plate on the other end of the shaft. When embedded in concrete with the nail-shaped head exposed, the anchor is available for engagement with bail lift clutches. When embedded in concrete with the perforated plate end exposed, the anchor is available for engagement with ring clutches. In this manner, one universal anchor may be used regardless of the type of clutch available.

Abstract: A computer system employing a microkernel executes two different tasks, e.g., operating systems, yet uses common shared libraries. Rather than each task setting up its own libraries, during compile a global offset table is set up for each task so that the tasks can use common shared libraries. An abstractions layer is established to allow the tasks to share the global offset table, and thus to use common shared libraries. Threading package related services are resolved via the abstractions mechanism. This abstractions mechanism includes services implemented as operating system abstractions, and include thread creation, exit from a thread, etc. Abstracted functions utilize pointers to runtime environment-specific functions, and are utilized by the task's runtime environment.

Abstract: A tool block holds an integrated lead suspension during assembly. The tool block has a number of features for precisely positioning the integrated lead suspension while transducer heads are being mechanically and electrically connected to it. The most critical feature is a movable datum clamping pin which is positioned to precisely engage a mount plate on the integrated lead suspension. Other features of the tool block include a platform support, a locating hole, a platform clamp and a pivot arm.

Abstract: A specialized hardware engine implementing a pipeline technique allows a host graphic workstation to process and display bit mapped images in real time. This hardware engine is capable to apply a pixel by pixel transformation to a wide variety of images (e.g. monoband or three bands such as RGB with 1/2/4/8/12 bit per pixel) and displaying the resulting images that should be zoomed, shrinked, rotated, panned and moved at a high display rate. All the hardware blocks in this pipeline are fully programmable by an onboard microprocessor to allow maximum image manipulation flexibility and a wide range of image functions. Supported image functions include discrete and smooth image size magnification and reduction by bilinear interpolation, 2D/3D image transformation with perspective, image panning, scrolling and moving, color transformation by color look up table (CLUT) with support of a wide variety of pixel format images, and RGB images processing at the same speed as monoband images processing.

Abstract: To protect integrated circuits as efficiently as possible against electrostatic discharges, by putting a diode in avalanche mode without untimely triggering of this avalance mode by overvoltages of non-electrostatic origin, the following solution is proposed: through an insulated gate surrounding the cathode of the diode, the threshold for transition into avalanche mode of the diode is modified according to the slope of the overvoltages appearing at the terminal to be protected. The gate is connected to the terminal by an integrating circuit in such a way that the overvoltages are applied to the gate with a certain delay, inducing a potential difference between the cathode and the gate which is all the greater as the front of the overvoltage is steep. The avalanche triggering threshold is higher in the latter case than in the former one, and it is thus distinguish between overvoltages of diverse origins.