Abstract: A pallet accelerator transfers workpiece pallets at high speeds from a pre-stop to a work stop in a conveyorized manufacturing line. While a workpiece is being processed in the work stop position, a pallet is released from a release stop into the pallet accelerator at the pre-stop position. The pallet accelerator has two fingers which engage the pallet. The pallet accelerator is pneumatically actuated to accelerate the pre-stop pallet forward while simultaneously pushing the work stop pallet downstream out of the work stop. The pallet accelerator resets for the next pallet released from the release stop while the pallet at the work stop is processed.

Abstract: A method and system are disclosed that utilize the expressiveness of hardware description languages for automatically adjusting counting rates of instrumentation within a simulation model of a digital circuit design, during simulation of said digital circuit design. According to the present invention a design entity that will be incorporated into a simulation model of a digital circuit design is described utilizing a hardware description language. The design entity operates, during simulation, in conformity with a design cycle that consists of a multiple of a simulator cycle. Next, an instrumentation entity is described utilizing the same hardware description language. The description of the instrumentation entity contains logic to detect occurrences of a count event that occurs in conformity with the design cycle during simulation.