Abstract: A system enabled for reliable and ordered data communication between two sets of nodes with atomic multi-point delivery and multi-point transmission, for example, extending TCP/IP is described hereon. The transmission control protocol (TCP/IP) is intended for reliable host-to-host communication [RFC 793]. The invention extends TCP's notion of host-to-host communication to symmetric group-to-group communication maintaining TCP specifications for data traffic between the groups. The current definition of, two endpoints of a TCP connection is extended to two groups of endpoints, communicating over the connection. End-points of a connection terminate at group nodes. When multiple nodes must be delivered with data, the delivery is performed atomically. Of data originating multiple nodes, optionally, a single data instance is transmitted. Each endpoint is comprised of a receiveHead and a sendHead operating independently.

Abstract: A system and method for voice recognition is disclosed. The system enrolls speakers using an enrollment voice samples and identification information. An extraction module characterizes enrollment voice samples with high-dimensional feature vectors or speaker data points. A data structuring module organizes data points into a high-dimensional data structure, such as a kd-tree, in which similarity between data points dictates a distance, such as a Euclidean distance, a Minkowski distance, or a Manhattan distance. The system recognizes a speaker using an unidentified voice sample. A data querying module searches the data structure to generate a subset of approximate nearest neighbors based on an extracted high-dimensional feature vector. A data modeling module uses Parzen windows to estimate a probability density function representing how closely characteristics of the unidentified speaker match enrolled speakers, in real-time, without extensive training data or parametric assumptions about data distribution.

Abstract: Apparatus and method for detecting an analyte in a sample based on optical interference. The apparatus includes a light source, detector unit and one or more disposable detector tips. The apparatus also includes an optical coupling assembly that couples light from the source to the detector tips, and from the detector tips to the detector unit.

Abstract: An optical pattern generator includes one or more multi-faceted rotating optical elements that introduce an offset that is rotation insensitive. The component that generates the offset is rotationally symmetric around the rotational axis of the optical element. Thus, as the optical element rotates, the effect of the offset component does not change. In addition, rotating optical elements may be designed to counteract unwanted optical effects of each other.

Abstract: A container for locally determining a container state using a state device. The state device detects unexpected events by comparing expected event information with actual event information related to a container condition. The container condition includes, for example, environmental conditions, logistical or location conditions, and physical or security conditions. Thus, the container is able to intelligently monitor its state and raise an alert without intervention from a central system. The container can also be programmed and reprogrammed with updated logic, states, and/or expected event information. A sensor in the state device gathers input information for comparison to expected event information. A communication port in the state device receives event information. For example, a GPS (Global Positioning System) receiver can determine a current location for comparison to an expected location at the current time.

Abstract: The present invention discloses an improved information security system and method. A polymorphic engine is used to enhance the security features of a software application and the data generated by or made available to the application and/or the operating system. The polymorphic engine operates to randomly alter the standard executable code of the original application while preserving its functional characteristics. Each polymorphed instance of the application differs from any other instance of the same application in form only. Various other security features operate to protect the polymorphic engine itself and/or the polymorphed code generated therefrom. These other security features include: just-in-time instruction code decryption; virtual CPU instruction code pre-processing; call mutation; stack manipulation; secure hook-capture of device input; secure display device output; application level decryption of encrypted hardware data streams; and a dynamic, randomly configured graphical keypad interface.

Abstract: A system and a method are disclosed for synchronizing folders between one or more layers of folders. It includes selecting layers to link together, comparing folders in the selected layers using an immutable identifier, parsing the folders of each of the selected layers into fields, comparing the fields of parsed folders of the selected layers, and determining whether to synchronize the folders of the selected layers based on conflict rules triggered in response to the comparison of the fields of the parsed folders. Also disclosed is a system and method of merging two or more folders in a network into a single folder. It includes comparing entries between folders to identify duplicate entries, grouping the identified duplicate entries in each folder, generating a matrix from the duplicates grouping and assigning each matrix entry a value, and matching the matrix entries based on the assigned values to determine an extent to merge an identified duplicate entry.

Abstract: A system and method in accordance with the invention reliably and non-intrusively identifies various conditions of a network. In particular, an embodiment of the invention can identify an operating system, including version and patch level, and a service, including version and patch level, of a remote host on the network. Using this information, an embodiment of the invention can then reliably identify a vulnerability condition of the network. In some embodiments, the operating system and service information can be used to identify a trojan application, unlicensed software use, security policy violations, or even infer vulnerabilities that are yet unknown.

Abstract: A multi-mode latch timing circuit has a first set of latches and a second set of latches in each logical path. In a first mode of operation, first and second phase clock signals are provided so that the latch timing circuit functions as a two-phase non-overlapping transparent latch timing circuit. In a second mode of operation, the first set of latches is held in a transparent state in some or all of the logical paths, thereby reducing clock power. In one embodiment, the first set of latches in each long path is held in a transparent state while the second phase clock signal is supplied to the second set of latches. In one embodiment, the first set of latches in each short path is held in a transparent state while a second phase clock signal comprised of shortened duty cycle pulses is supplied to the second set of latches.

Abstract: Some computer operating systems do not permit application programs to perform certain tasks. If there is a desire to perform a forbidden task, a virtual partition (228) is created (610) in a storage device (108), such as a hard disk drive, associated with the computer system (100). The virtual partition (228) is stored as a file within the file system of the storage device (108). Operating system files (414) are installed in the virtual partition (228), and the storage device (108) is configured (616) to boot the computer system (100) using the operating system in the virtual partition. When the task is complete, the computer system (100) is configured to boot using the operating system other than the one in the virtual partition.

Abstract: A processing system includes an arithmetic logic unit (ALU) sub-system that allows data associated with a prior instruction to be preserved for use with a next instruction or subsequent instruction without having to reload the value using an intermediate register. The ALU sub-system includes a pair of ALUs communicatively cross-coupled with a pair of accumulators. The processing system also includes a data selector coupled to the ALU sub-system for use with memory contention prediction. The data selector includes a constant generator that controls storage of data associated with a previous instruction in a bypass element, and a selector to choose between data from a databus element and data stored in the bypass element.

Abstract: A system and method for sharing access to an internet protocol (IP) network among multiple internet service providers (ISPs) uses multiprotocol label switching (MPLS). End-users are coupled to a broadband customer access network. Each end-user is also associated with at least one of the ISPs. An aggregation router interfaces the customer access network with a network backbone. The network backbone includes a border router for interfacing between the network backbone and the network of an ISP. When the border router is activated, it creates a forwarding equivalency class (FEC) corresponding to the ISP. The border router stores a label for the FEC and the interface for reaching the ISP in an FEC table. The border router advertises the label binding for the FEC to all upstream nodes. An intermediate node receiving the label binding creates its own FEC table, associates a new label with the FEC, and advertises the new label binding to its upstream nodes.

Abstract: A method and apparatus operating within an object-oriented virtual memory management system. In the virtual memory management system, each page is referenced by traversing a series of mapping tables. Each mapping table is associated with one of a plurality of Partitioned Memory Objects (PMOs). Each PMO includes a plurality of MORs (Memory Object References). PMOs and NSKMPage data structures are collectively referred to as memory objects. When a memory object is duplicated (also called a “copy on write” or a “virtual copy”), the actual copy of the duplicated memory object is deferred until a write to the memory object actually occurs. MORs have a VCState field, which can have values of VCOriginal, VCDuplicate, VCSubdupFull, or VCSubdupPart. During a copy on write operation, a VCState of a MOR referring to the duplicated memory object is set to “VCDuplicate” and set to point to the memory object that was copied.

Abstract: A drive roller for a belt-driven tape cartridge is molded of composite polymeric material in a single step to include outer segment and inner segment integrally formed together with a radial web segment between the outer and inner segments to provide highly concentric operating surfaces on the outer segment and in the inner segment. Electrical conductivity throughout the molded drive roller is provided by including in the composite material a quantity of carbon powder, and selective shrinkage of the composite material during cooling from molding temperatures provides desirable bearing surface within the inner bore through the inner segment. Thrust bearing surfaces at the ends of the inner segment engage mating bearing surfaces that include lubricant traps to inhibit migration of lubricant away from the bearing surfaces of the drive roller.

Abstract: A method and apparatus for generating circuitry to initialize memory contained in an integrated circuit generated from a description for a programmable logic device is provided. The initialization bits in the bit stream used to program the programmable logic device are identified and extracted. Using these initialization bits and a set of selectable control circuitry options, initialization control logic is generated. Data initialization logic is also generated using the extracted initialization bits.

Abstract: A device for converting punch changing in punching machines from manual to quick and automatic comprises: a stator element, which can be inserted in a corresponding and conventional seat provided in the machine and supports a plurality of punches which are arranged vertically in a circular pattern and can slide in corresponding hollow seats; a rotor element, which can be rotated by corresponding elements coaxially inside the stator and is eccentrically provided with a pusher which can be aligned, through gradual rotations of the rotor element, so as to be coaxially vertical above each one of the punches; the rotor element can also be moved vertically by an extent inside the stator, in contrast with elastic elements and guided by stem-like elements which are rigidly coupled to the stator element.

Abstract: An assembly, and an associated method, that facilitates restoration of data to a computer data storage subsystem subsequent to failure and repair of the subsystem. An identification indicia memory contains an up-to-date listing of the file name, or other identification indicia, of data stored at the data storage subsystem. The listing is accessed and used to retrieve a copy of data stored at the storage subsystem prior to its failure. Recovery operations write the copy of the data to the repaired or replaced storage medium of the data storage subsystem.

Abstract: This invention concerns to an axial flow turbine referred as to an hydroreactor, to take advantage of the kinetic energy from the water in relative depth places in rivers, estuaries or inlets, where the water streams are meaningful for the production of electric power.

Abstract: A voltage level shift system transitions a voltage signal between two components and includes a first inverter, a signal pass subsystem, a pull-up transistor, a second inverter, and a third inverter. The first inverter is coupled to the signal pass subsystem. The signal pass subsystem is coupled to the pull-up transistor, the second inverter, and the third inverter. The signal pass subsystem includes a first passgate and a second passgate. When an input voltage transitions from a logic low to a logic high, the first inverter inverts the logic high input signal to a logic low and passes this signal through the passgate subsystem. The second inverter receives the logic low signal and immediately inverts it to transition the output signal from a low logic to a logic high. The logic high output signal, turns off the pull-up transistor.

Abstract: A bus bridge circuit employs a dynamic allocation scheme that allows read transactions to be pipelined without deadlock and without the need for permanently reserving multiple buffer slots for read response transactions. The bus bridge circuit associates input and output buffers with a node and includes a state machine to monitor the number and type of transaction packets currently in slots that make up the buffers. In particular, the state machine monitors the number of transaction packets loaded in the output buffer slots, the number of outstanding read transactions for the node, and the number of read response transactions currently loaded in the output buffer. The state machine then allows the node to load a READ or WRITE transaction only if the monitored data indicates at least one of the buffer slots will be available to service a READ RESPONSE subsequently loaded by the node.