Patents Represented by Attorney Ferdinand M. Romano
  • Patent number: 6930006
    Abstract: A semiconductor device having improved dielectric properties and a method for fabricating a semiconductor device. A semiconductor device includes a semiconductor layer suitable for device formation. A dielectric layer formed over the semiconductor layer has first and second opposing surfaces, a first surface region along the first surface and a second surface region along the second surface. A mid region is positioned between the first and second surface regions. The material of the dielectric layer includes a species having a concentration greater in the mid region than along the first opposing surface. The dielectric layer may be incorporated in a field effect transistor or a capacitor. According to a disclosed method an insulative layer is formed with two or more elements chemically bonded to one another. An additional species is introduced into the insulative layer in sufficient quantity to modify the net dielectric constant of the layer.
    Type: Grant
    Filed: May 13, 2002
    Date of Patent: August 16, 2005
    Assignee: Agere Systems Inc.
    Inventors: Konstantin K. Bourdelle, Yuanning Chen
  • Patent number: 6838717
    Abstract: A monolithic integrated circuit including a capacitor structure. In one embodiment the integrated circuit includes at least first and second levels of interconnect conductor for connection to a semiconductor layer and a stack of alternating conductive and insulative layers formed in vertical alignment with respect to an underlying plane. The stack is formed between the first and second levels of conductor. Preferably the stack includes a first conductive layer, a first insulator layer formed over the first conductive layer, a second conductive layer formed over the first insulative layer, a second insulator layer formed over the second conductive layer, and a third conductive layer formed over the second insulative layer, with the first and third conductive layers commonly connected.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: January 4, 2005
    Assignee: Agere Systems Inc.
    Inventors: Allen Yen, Frank Yauchee Hui, Yifeng Winston Yan
  • Patent number: 6750528
    Abstract: An integrated electronic device includes a semiconductor substrate layer having a major surface formed along a crystal plane. In one embodiment a first conductivity type region is formed in the substrate layer and a substantially monocrystalline semiconductor layer is deposited thereon. The deposited layer includes a first portion of a second conductivity type and a second portion of the first conductivity type formed over the first portion. The first portion and the first region form a pn junction. An upper-most substrate surface formed along a first plane and a first doped region of a first conductivity type is formed above the first plane. A second doped region of a second conductivity type is formed over the first doped region resulting in formation of a p-n junction in a second plane above the first plane. Electrical connection is provided to the first doped region with a conductor formed between the first and second planes.
    Type: Grant
    Filed: January 23, 2001
    Date of Patent: June 15, 2004
    Assignee: Agere Systems Inc.
    Inventor: Yih-Feng Chyan
  • Patent number: 6713409
    Abstract: A manufacturing method using a modular substrate-based processing scheme for producing semiconductor devices, provides multiple modular processing units which may be arranged together to form any of various cohesive processing units or individually or sequentially processed through standard semiconductor processing equipment. The cohesive processing units are processed unitarily providing for multiple modular processing units to be processed simultaneously. The modular processing units may be formed of a thick semiconductor substrate or a semiconductor substrate mounted on a further substrate such as a ceramic material. The modular processing units may each contain ribs, grooves, posts or other features to aid in handling and placement of the individual units.
    Type: Grant
    Filed: November 25, 2002
    Date of Patent: March 30, 2004
    Assignee: Agere Systems Inc.
    Inventors: Michael Antonell, Erik Cho Houge, Nitin Patel, Larry E. Plew, Catherine Vartuli
  • Patent number: 6680150
    Abstract: Sidelobe formation in photolithographic patterns is suppressed by non-rectangular, non-circular contact openings formed in attenuated phase shift photomasks. The contact openings may be diamond-shaped, star-shaped, cross-shaped, or various other shapes which include multiple vertices. The contact opening shapes may include only straight line segments or they may include rounded segments. The contact openings may be arranged in various relative configurations such as in arrays in which the contact openings are sized and spaced by sub-wavelength dimensions. A method for forming contact openings on a photosensitive film uses the attenuated phase shift photomask to form a contact pattern free of pattern defects. A computer readable medium includes instructions for causing a photomask manufacturing tool to generate the attenuated phase-shift photomask.
    Type: Grant
    Filed: May 25, 2001
    Date of Patent: January 20, 2004
    Assignee: Agere Systems Inc.
    Inventors: James W. Blatchford, Jr., Omkaram Nalamasu, Stanley Pau
  • Patent number: 6657302
    Abstract: A structure and method for fabricating integrated circuits with improved electrical performance. The structure comprises electronic devices formed along a semiconductor surface, a first upper level of interconnect members over the semiconductor surface, a lower level of interconnect members formed between the semiconductor surface and the first upper level, and insulative material positioned to electrically isolate portions of the upper level of interconnect members from one another. The insulative material comprises a continuous layer extending from within regions between members of the upper interconnect level to within regions between members of the lower interconnect level and is characterized by a dielectric constant less than 3.9. The method begins with a semiconductor layer having electronic device regions thereon. A first insulative layer is deposited over the electronic device regions and a lower level of interconnect members is formed over the first insulative layer.
    Type: Grant
    Filed: December 17, 1999
    Date of Patent: December 2, 2003
    Assignee: Agere Systems Inc.
    Inventors: Huili Shao, Susan Clay Vitkavage, Allen Yen
  • Patent number: 6633032
    Abstract: The present invention relates to a device for testing particles for composition and concentration. The device includes a particle counter, a collector screen, and a mass spectrometer. In one embodiment, the collector screen is positioned to receive particles received by the particle counter, and the mass spectrometer is positioned to receive counted particles retained on the collector screen.
    Type: Grant
    Filed: November 30, 2000
    Date of Patent: October 14, 2003
    Assignee: Agere Systems Inc.
    Inventors: Erik Cho Houge, John Martin McIntosh, Fred Anthony Stevie, Steven Barry Valle, Catherine Vartuli
  • Patent number: 6625250
    Abstract: A reflective lens with at least one curved surface formed of polycrystalline material. In an example embodiment a lens structure includes a substrate having a surface of predetermined curvature and a film formed along a surface of the substrate with multiple individual members each having at least one similar orientation relative to the portion of the substrate surface adjacent the member such that collectively the members provide predictable angles for diffraction of x-rays generated from a common source. A system is also provided for performing an operation with x-rays. In one form of the invention the system includes a source for generating the x-rays and a polycrystalline surface region having crystal spacings suitable for reflecting a plurality of x-rays at the same Bragg angle along the region and transmitting the reflected x-rays to a reference position.
    Type: Grant
    Filed: December 19, 2000
    Date of Patent: September 23, 2003
    Assignee: Agere Systems Inc.
    Inventor: Erik Cho Houge
  • Patent number: 6606371
    Abstract: A reflective lens with at least one curved surface formed of polycrystalline material. In one embodiment, a lens structure includes a substrate having a surface of predetermined curvature and a film formed along a surface of the substrate with multiple individual members each having at least one similar orientation relative to the portion of the substrate surface adjacent the member such that collectively the members provide predictable angles for diffraction of x-rays generated from a common source. A system is also provided for performing an operation with x-rays. In one embodiment, a system includes a source for generating the x-rays, a polycrystalline surface region having crystal spacing suitable for reflecting a plurality of x-rays at the same Bragg angle along the region, and transmitting the reflected x-rays to a reference position.
    Type: Grant
    Filed: December 19, 2000
    Date of Patent: August 12, 2003
    Assignee: Agere Systems Inc.
    Inventors: Michael Antonell, Erik Cho Houge, John Martin McIntosh, Larry E. Plew, Catherine Vartuli
  • Patent number: 6588437
    Abstract: Apparatus for removal of material in reactions having limited solubility and diffusion. An exemplary system removes unwanted material from the surface of a semiconductor wafer. A flow apparatus is provided for removal of material from a work piece having at least one reaction region containing removable material. The apparatus may include first and second assemblies positionable in spaced-apart relation to form a zone extending between the two assemblies for movement of gaseous material. The first assembly may include a fixture positioned to receive the work piece with the reaction region of the work piece disposed in the zone to allow movement of the gaseous material thereover. A flow assembly is configured to transfer into the zone a gas comprising a condensable material and a reacting species. In another embodiment a system for removal of material from a workpiece includes a chamber, a flow component and a support apparatus.
    Type: Grant
    Filed: November 14, 2000
    Date of Patent: July 8, 2003
    Assignee: Agere Systems Inc.
    Inventor: Gregg S Higashi
  • Patent number: 6585830
    Abstract: An unwanted tungsten film deposit on a Chemical Vapor Deposition chamber is cleaned by adding a mixture of at least two cleaning gases into the chamber at a predetermined temperature and pressure and in contact with said chamber walls for a sufficient length of time. The cleaning gases and reacted tungsten species are removed from the chamber by vacuum, and unreacted cleaning gases are removed by purging the chamber with an inert gas. At least one cleaning gas is selected from the group consisting of bromomethane, dibromomethane, bromoform and mixtures thereof. The temperature of the chamber is preferably at least about 300 degrees Celsius. The cleaning gases in the chamber are at a pressure in the range from about 100 to 200 Torr and the chamber is purged at a pressure in the range from about 200 to 500 Torr.
    Type: Grant
    Filed: November 30, 2000
    Date of Patent: July 1, 2003
    Assignee: Agere Systems Inc.
    Inventors: Nace Layadi, Sailesh Mansinh Merchant, Simon John Molloy
  • Patent number: 6569690
    Abstract: Method for fabricating a structure. According to an exemplary embodiment, a structure is made by forming a layer of removable material with a first surface spaced a part from a second surface. The first surface is formed along a first region from which the material is removable. The first surface is altered by removal of material from the layer. Removed material from the first surface is monitored to detect fluctuations in a variable of composition in the layer, and removal of material from the first surface is terminated when the composition of monitored material meets a predetermined criterion. In an alternate embodiment a variable characteristic is imparted to a layer of material as a function of layer thickness and an operation is performed on the layer resulting in removal of material. Samples of removed material are monitored for variation in the characteristic and the operation is modified when a variation conforms with a criterion.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: May 27, 2003
    Assignee: Agere Systems Guardian Corp
    Inventors: Erik Cho Houge, Isik C. Kizilyalli, John Martin McIntosh, Fred Anthony Stevie, Catherine Vartuli
  • Patent number: 6548892
    Abstract: A porous insulator material and method of manufacturing. The material comprises oxygen, silicon and hydrogen characterized by a density less than 2 g/cc. Alternately, the porous insulator material is characterized by a refractive index less than 1.45 for light at a wavelength between 633 nm and 673 nm, or by a Young's modulus less than 45 GPa. A method for manufacturing a semiconductor device includes providing a semiconductor layer with an upper surface for device formation and forming multiple levels of interconnect over the semiconductor layer, each level including a plurality of members. The members are electrically isolated from other members by decomposition of TEOS to form a porous layer between at least some of the members.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: April 15, 2003
    Assignee: Agere Systems Inc.
    Inventors: Kurt George Steiner, Susan Clay Vitkavage
  • Patent number: 5757036
    Abstract: A four-region semiconductor device (that is, a p-n-p-n or n-p-n-p device) including at least one further region utilizes integral FET structure for diverting carriers away from an interior region of the device and shunting them to a main current-carrying electrode of the device, whereby the device is provided with a turn-off capability. The device requires only a small amount of energy for its turn-off control gate, and utilizes a high percentage of its semiconductor body for carrying current through the device. High speed turn-off is achieved in a particular embodiment of the device.
    Type: Grant
    Filed: July 15, 1994
    Date of Patent: May 26, 1998
    Assignee: Harris Corporation
    Inventor: Victor Albert Keith Temple
  • Patent number: 5580816
    Abstract: A method for electrically isolating semiconductor devices in an integrated circuit structure with high field threshold, low defect level regions. The semiconductor structure includes a device layer predominantly comprising lattice silicon with a surface suitable for device formation. Multiple device regions are defined and field regions are defined for electrically isolating the device regions from one another. Dopant species are implanted to create a channel stop adjacent two of the device regions. The implant is of sufficient energy and concentration to impart within the device layer nucleation sites of the type known to result in stacking faults during oxide growth conditions. A thickness of thermally grown silicon dioxide is formed in the field regions by first thermally processing the integrated circuit structure to remove nucleation sites from the device layer and form a minor portion of the field oxide thickness.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: December 3, 1996
    Assignee: Harris Corporation
    Inventors: Donald F. Hemmenway, Lawrence G. Pearce
  • Patent number: 5332931
    Abstract: A differential comparator with inputs switched and capacitively coupled to inverters which have capacitive cross-coupling feedback for a latching operation. The inverters also have direct switched feedback for autozeroing. The inputs further have a shorting switch between the input switches and the coupling capacitors for offset compensation. Complementary operation of the switches provides precharge and evaluation phases of operation. During precharge the inputs are applied to the input coupling capacitors and the inverters are autozeroed; during evaluation the inputs are transferred to the inverters through the coupling capacitors and the outputs feedback positively through the cross-coupling capacitors to latch the pair of inverters.
    Type: Grant
    Filed: June 24, 1991
    Date of Patent: July 26, 1994
    Assignee: Harris Corporation
    Inventors: Finbarr J. Crispie, Geert P. Rosseel
  • Patent number: 5312262
    Abstract: A mechanism structure for decoupling prong and socket type electrical connections, particularly for circuit board cards and their connections to receptacle-connectors in chassis-like housings. In one embodiment, the decoupling structure comprises a plate, a rotatable rod supported by the plate, an actuating lever attached to one end of the rod, and a cam attached along the rod. In application, the lever is pushed or pulled causing the cam to apply a force separating the circuit board from the receptacle connection so as to reduce or avoid torsional forces when disconnecting the board from the receptacle.
    Type: Grant
    Filed: December 23, 1992
    Date of Patent: May 17, 1994
    Assignee: Harris Corporation
    Inventor: Jeff L. Bublitz
  • Patent number: 5276633
    Abstract: A sine/cosine generator with coarse and fine angles having compressed sine and cosine read only memories (ROMS) by use of symmetry of coarse angles about .pi./4 and, optionally, symmetry of fine angles about 0. The output of the ROMs directly feed multiplexers for utilization of the compressed storage. Addressing of complementary coarse angles is with one's complementing of the address and of complementary fine angles is with two's commplementing of the address. Fine sines and cosines are stored in recoded version for direct use in multipliers for computations using the sum of angles formulas.
    Type: Grant
    Filed: August 14, 1992
    Date of Patent: January 4, 1994
    Assignee: Harris Corporation
    Inventors: James G. Fox, William R. Young, David B. Chester
  • Patent number: 5272104
    Abstract: A semiconductor-on-insulator structure incorporating a layer of diamond material and method for preparing such. The structure comprises a layer containing diamond material and having a first surface. A layer of silicon nitride is formed on the first surface and a layer of semiconductor material is positioned over the silicon nitride layer. In one embodiment of the method there is provided a removable deposition surface. A layer of crystalline diamond material is formed on the deposition surface. A first surface of the diamond material is separated from the deposition surface. The structure is useful for formation of integrated circuits thereon.
    Type: Grant
    Filed: March 11, 1993
    Date of Patent: December 21, 1993
    Assignee: Harris Corporation
    Inventors: Gregory A. Schrantz, Jack H. Linn, Richard W. Belcher
  • Patent number: 5266135
    Abstract: A bonding method including pressing a pair of slices together with a liquid oxidant therebetween and subjecting the pair of slices to a temperature to bond the slices together. Preferably a liquid oxidant is applied to one of the slices before they are pressed together and then dried. The heating step for bonding is carried out at a sufficiently high temperature of at least 1100.degree. C. to make the slices pliable so as to comply with each other during the bonding step.
    Type: Grant
    Filed: February 12, 1992
    Date of Patent: November 30, 1993
    Assignee: Harris Corporation
    Inventors: John P. Short, Craig J. McLachlan, George V. Rouse, James R. Zibrida