Patents Represented by Attorney, Agent or Law Firm Ferdinand Romano
  • Patent number: 6764930
    Abstract: A metal oxide semiconductor (MOS) capacitor formed according to a process in which Fermi level enhanced oxidation is suppressed by the introduction of nitrogen impurities into an N-doped impurity region is formed to utilize the N-doped impurity region as a lower electrode and includes a capacitor dielectric having a reduced thickness with respect to other portions of the thermal oxide film formed over N-doped impurity regions. The capacitor is highly linear and includes a high capacitance density. The process used to form the capacitor includes thermally oxidizing a substrate such that an oxide film is formed to include multiple thicknesses including an enhanced oxide growth rate producing an oxide film of increased thickness in N-doped impurity regions and a section within nitrogen-doped impurity portions of the N-doped impurity region in which the enhanced oxidation growth is suppressed and the film formed in this region includes a desirably reduced thickness.
    Type: Grant
    Filed: September 26, 2001
    Date of Patent: July 20, 2004
    Assignee: Agere Systems Inc.
    Inventors: Jerome Tsu-Rong Chu, Sidhartha Sen
  • Patent number: 5307023
    Abstract: A non-linear current mirror amplifier includes a master diode-connected transistor in series with a resistor to provide a forward diode bias and a resistive drop. A slave transistor is forward biased by the forward diode bias and the resistive drop. A current splitter applies a fraction of an input current to the master diode-connected transistor.
    Type: Grant
    Filed: October 16, 1992
    Date of Patent: April 26, 1994
    Assignee: Harris Corporation
    Inventor: Otto H. Schade, Jr.
  • Patent number: 5287068
    Abstract: An amplifier includes first and second amplifying stages with the first amplifying stage having an inverting input, a non-inverting input and an intermediate output node at which is produced a signal responsive to signals applied to the inverting and non-inverting inputs. The second amplifying stage has an input connected to the intermediate output node and an output connected to an amplifier output terminal. A selectively enabled transmission gate is connected in series with a capacitor between the input and the output of the second amplifying stage. The selectively enabled transmission gate means, when enabled, functions as a resistance which in combination with the capacitor provides frequency compensation for the amplifier. When the transmission gate is disabled, it functions to disconnect one side of the capacitor and eliminates its loading effect on the amplifier stage.
    Type: Grant
    Filed: August 27, 1992
    Date of Patent: February 15, 1994
    Assignee: Harris Corporation
    Inventors: John A. Olmstead, Salomon Vulih
  • Patent number: 4951252
    Abstract: A digital memory system of the type which includes an amplifier transistor connected to provide an amplified bit line signal corresponding to the state of a selected memory cell. A bit line pull-up transistor is positioned to function as a bit line current source and as a load device for the amplifier transistor. The amplifier transistor is connected between the pull-up transistor and the bit line and an output node positioned between the pull-up and amplifier transistors provides the amplified bit line signal corresponding to the state of a selected memory cell.
    Type: Grant
    Filed: October 25, 1988
    Date of Patent: August 21, 1990
    Assignee: Texas Instruments Incorporated
    Inventors: William A. White, Albert H. Taddiken