Patents Represented by Attorney, Agent or Law Firm Fernandez & Assoc., LLP
  • Patent number: 7970699
    Abstract: The invention relates to methods that create and update a centralized and searchable database of lenders' underwriting and pricing guidelines that can be utilized by the consumer and to a system that matches the consumer's qualifications and needs to the best available loan products with associated rate pricing.
    Type: Grant
    Filed: March 27, 2006
    Date of Patent: June 28, 2011
    Assignee: Loan Insights, Inc.
    Inventors: William Bramlage, Jonathan Strike
  • Patent number: 6735689
    Abstract: Penalty for taking branch in pipelined processor is reduced by pre-calculating target of conditional branch before branch is encountered, thereby effectively converting branches to jumps. During program execution, pipeline penalty is reduced effectively to that of unconditional jump. Offset bits are replaced in a conditional branch with index bits based on addition of offset bits and a program counter value. Scheme reduces need for cycle to calculate target of taken branch. Scheme may be applied during cache fill or dead cycle when taken branch is read from pipelined cache.
    Type: Grant
    Filed: May 1, 2000
    Date of Patent: May 11, 2004
    Assignee: Raza Microelectronics, Inc.
    Inventors: Thomas W. S. Thomson, Jack Choquette
  • Patent number: 6708282
    Abstract: In complex systems, the arrival of data to a computation component is difficult to predict. A method of synchronizing the initiation of computation with the reception of its input data is disclosed. The method allows the input data and computation initiation commands to arrive in any order. The method is dynamically adjustable allowing for varying numbers of data inputs.
    Type: Grant
    Filed: September 5, 2000
    Date of Patent: March 16, 2004
    Assignee: Raza Microelectronics, Inc.
    Inventors: Dominic Paul McCarthy, Jack Choquette
  • Patent number: 6686774
    Abstract: A method and system for high speed bussing in microprocessors and microelectronic devices is disclosed. The method and system implement a type of differential bus with distributed bus pre-charge units designed to decrease bus pre-charge time. The method and system utilize a universal self-tracking clock signal to determine the minimum required bus pre-charge time. The time saved by decreasing the bus pre-charge time can be directly applied to the bus evaluation period thereby increasing system performance and reliability.
    Type: Grant
    Filed: July 19, 2001
    Date of Patent: February 3, 2004
    Assignee: Raza Microelectronics, Inc.
    Inventor: Tejvansh Singh Soni